Patents by Inventor Noritaka Yamashita
Noritaka Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119469Abstract: The feature extraction means 81 extracts a feature of data from at least one data of market data and test data. The data selection means 82 selects one or more other data containing a feature corresponding to the extracted feature of the one data. The complementary data calculating means 83 calculates complementary data that complements the market data or the test data from the one data and the selected other data. The integrated data generation means 84 generates integrated data that integrates the calculated complementary data with at least one or both of the market data and the test data.Type: ApplicationFiled: February 24, 2021Publication date: April 11, 2024Applicant: NEC CorporationInventor: Noritaka YAMASHITA
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Publication number: 20240104273Abstract: The surrogate model construction means 81 constructs a surrogate model that simulates behavior of an analysis target, using operation data of the analysis target as training data. The surrogate model selection means 82 selects the surrogate model that is judged to best reproduce the behavior of the analysis target by the operation data according to verification contents, under specified condition, from the operation data of the analysis target. The verification means 83 verifies the analysis target using the selected surrogate model.Type: ApplicationFiled: February 12, 2021Publication date: March 28, 2024Applicant: NEC CorporationInventor: Noritaka Yamashita
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Publication number: 20230092026Abstract: The present invention provides a processing apparatus (10) including: a determination unit (12) determining a predetermined vehicle state and a predetermined ambient environment, based on user vehicle data indicating a vehicle state and an ambient environment when a user uses a vehicle; a computation unit (13) computing a degree of similarity between the predetermined vehicle state and the predetermined ambient environment, and a vehicle state and an ambient environment indicated by a vehicle running test scenario; and an output unit (14) outputting a computation result by the computation unit (13).Type: ApplicationFiled: March 19, 2020Publication date: March 23, 2023Applicant: NEC CorporationInventors: Noritaka YAMASHITA, Kenji SOBATA, Masayuki SAKATA, Yuki CHIBA
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Publication number: 20220283798Abstract: The mobility control system 80 is mounted on a mobility to be controlled and performs control according to the condition of the mobility. The software state detection unit 81 detects the state of software that controls the mobility. The control unit 82 performs a control to restrict the operating function of the mobility on the basis of the state of the software. Further, the software state detection unit 81 detects the version information or update status of the software as the state of the software, and the control unit 82 determines the function to be restricted on the basis of the state of the software.Type: ApplicationFiled: May 29, 2020Publication date: September 8, 2022Applicant: NEC CorporationInventor: Noritaka YAMASHITA
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Publication number: 20220250655Abstract: The mobility control system 80 is mounted on mobility to be controlled and performs control according to condition of the mobility. The communication state detection unit 81 detects a communication state with an external device. The control unit 82 performs the control to restrict an operating function of the mobility based on the communication state. The communication state detection unit 81 detects communication availability or communication speed status as the communication state. The control unit 82 determines the function to restrict based on the communication state.Type: ApplicationFiled: May 29, 2020Publication date: August 11, 2022Applicant: NEC CorporationInventor: Noritaka YAMASHITA
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Publication number: 20160081190Abstract: A printed wiring board includes a resin insulation layer, a conductive layer formed on a surface of the resin insulation layer and including NSMD pads, and a solder-resist layer formed on the resin insulation layer and having openings such that the openings are exposing the NSMD pads, respectively. The solder-resist layer includes a lower solder-resist layer formed on the surface of the resin insulation layer and an upper solder-resist layer formed on the lower solder-resist layer, and each of the openings has a lower opening portion formed in the lower solder-resist layer and an upper opening portion formed in the upper solder-resist layer such that the upper opening portion has a size which is greater than a size of the lower opening portion.Type: ApplicationFiled: September 11, 2015Publication date: March 17, 2016Applicant: IBIDEN CO., LTD.Inventors: Yasushi INAGAKI, Atsushi KONDO, Hiroyuki NISHIOKA, Noritaka YAMASHITA
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Patent number: 8848903Abstract: A side channel attack resistance evaluation apparatus includes: a measurement section that measures side channel information leaking from an encryption device to be evaluated; a noise removal section that removes noise from the measured side channel information using a band-pass filter (BPF); a passband determination section that determines the passband of the band-pass filter; and a DSCA (Differential Side-Channel Analysis) evaluation section that evaluates resistance against the differential side channel analysis. The passband determination section preferably has a DFT processing section and a power spectrum analysis section, or has a DFT processing and a DFA processing section.Type: GrantFiled: February 4, 2009Date of Patent: September 30, 2014Assignee: NEC CorporationInventors: Toru Hisakado, Noritaka Yamashita
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Patent number: 8842824Abstract: An encryption processing circuit capable of inhibiting leakage of secret information from bit transitions of a register while inhibiting an increase in performance/area ratio is provided. N (N is an integer equal to 2 or greater) sets, each of which including an encryption block and a register, are included, wherein an encryption block of an i-th set performs encryption in a certain step on plain text stored in the register of the i-th set or intermediate data stored in the register of the i-th set obtained from the plain text and the intermediate data obtained by the encryption is stored in the register of an (i+1)-th set and the encryption block of an N-th set performs the encryption in the certain step on plain text stored in the register of the N-th set or intermediate data stored in the register of the N-th set obtained from the plain text and the intermediate data obtained by the encryption is stored in the register of a first set.Type: GrantFiled: November 27, 2012Date of Patent: September 23, 2014Assignee: Nec CorporationInventor: Noritaka Yamashita
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Publication number: 20140112468Abstract: An encryption processing circuit capable of inhibiting leakage of secret information from bit transitions of a register while inhibiting an increase in performance/area ratio is provided. N (N is an integer equal to 2 or greater) sets, each of which including an encryption block and a register, are included, wherein an encryption block of an i-th set performs encryption in a certain step on plain text stored in the register of the i-th set or intermediate data stored in the register of the i-th set obtained from the plain text and the intermediate data obtained by the encryption is stored in the register of an (i+1)-th set and the encryption block of an N-th set performs the encryption in the certain step on plain text stored in the register of the N-th set or intermediate data stored in the register of the N-th set obtained from the plain text and the intermediate data obtained by the encryption is stored in the register of a first set.Type: ApplicationFiled: November 27, 2012Publication date: April 24, 2014Applicant: NEC CORPORATIONInventor: Noritaka Yamashita
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Publication number: 20100322298Abstract: A side channel attack resistance evaluation apparatus includes: a measurement section that measures side channel information leaking from an encryption device to be evaluated; a noise removal section that removes noise from the measured side channel information using a band-pass filter (BPF); a passband determination section that determines the passband of the band-pass filter; and a DSCA (Differential Side-Channel Analysis) evaluation section that evaluates resistance against the differential side channel analysis. The passband determination section preferably has a DFT processing section and a power spectrum analysis section, or has a DFT processing and a DFA processing section.Type: ApplicationFiled: February 4, 2009Publication date: December 23, 2010Applicant: NEC CORPORATIONInventors: Toru Hisakado, Noritaka Yamashita
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Publication number: 20100246808Abstract: Provided is a side channel attack tolerance evaluation device capable of evaluating the propriety of the estimation of an encryption algorism, processing timing, and determination of a processing sequence of the encryption algorism using side channel information. The side channel attack tolerance evaluation device, which performs evaluation of tolerance to a side channel attack by using side channel information leaking from an encryption device, is provided with a storage unit (character data storage device), a measurement unit (side channel information measurement device), and a processing unit (side channel attack tolerance evaluation unit). The storage unit stores side channel information that has been previously acquired by executing a predetermined encryption algorithm in an encryption device or information obtained by applying predetermined processing to the side channel information. The measurement unit measures the side channel information generated from an encryption device to be evaluated.Type: ApplicationFiled: December 4, 2008Publication date: September 30, 2010Applicant: NEC CorporationInventors: Toru Hisakado, Noritaka Yamashita