Patents by Inventor Norito Hibino

Norito Hibino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7586788
    Abstract: Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage according to adjusting signals. To make the internal voltage close to its expected value, a voltage adjusting circuit outputs adjusting signals in accordance with cell currents that flow through the evaluation memory cells, respectively, in a read operation on the evaluation memory cells. As a result, the interval voltage that is shifted from its expected value due to variations in manufacturing conditions can automatically be set to the expected value by using the adjusting signals. Since an internal circuit operates on a correct internal voltage, operation margins can be increased. The yield of a nonvolatile semiconductor memory can thus be increased.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: September 8, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroshi Mawatari, Norito Hibino, Naoto Emi
  • Publication number: 20070133303
    Abstract: Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage according to adjusting signals. To make the internal voltage close to its expected value,- a voltage adjusting circuit outputs adjusting signals in accordance with cell currents that flow through the evaluation memory cells, respectively, in a read operation on the evaluation memory cells. As a result, the interval voltage that is shifted from its expected value due to variations in manufacturing conditions can automatically be set to the expected value by using the adjusting signals. Since an internal circuit operates on a correct internal voltage, operation margins can be increased. The yield of a nonvolatile semiconductor memory can thus be increased.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 14, 2007
    Inventors: Hiroshi Mawatari, Norito Hibino, Naoto Emi
  • Publication number: 20060053399
    Abstract: A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively wiring unit for tentatively arranging the regulator at the layout position candidates and tentatively laying out a power line, and a regulator layout position deciding unit for deciding a position of a tentative layout at which an area of the power line that is tentatively laid out is the smallest as the layout position of the regulator.
    Type: Application
    Filed: December 20, 2004
    Publication date: March 9, 2006
    Applicant: Fujitsu Limited
    Inventors: Hiroyuki Honda, Toshio Arakawa, Hiroshi Mawatari, Norito Hibino, Kouji Arai, Keigo Tada, Fukuji Kihara