Patents by Inventor Norito Umehara
Norito Umehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6784022Abstract: A method of producing semiconductor devices including the steps of providing a semiconductor wafer of substantially uniform thickness 22, providing a heat-radiating plate 22, and attaching the heat-radiating plate 20 to the semiconductor wafer. The assembled wafer and heat-radiating plate are diced into individual semiconductor integrated circuits having individual heat radiating plates attached thereto.Type: GrantFiled: April 11, 2002Date of Patent: August 31, 2004Assignee: Texas Instruments IncorporatedInventors: Norito Umehara, Masazumi Amagai
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Patent number: 6713851Abstract: The invention relates to an LOC type semiconductor device having improved heat radiation. The semiconductor device related to the present invention has a preferably metal heat-radiating element 7 that is in thermal contact with the surface opposite the principal surface of the semiconductor chip 3. One region of said heat-radiating element 7 is externally exposed from the package that encloses the semiconductor chip 3. The heat-radiating element 7 is in thermal contact with a metal pattern 12 that is formed on the substrate 10 on which the semiconductor device is mounted. The heat from the semiconductor chip is transferred to the mounting substrate 10 side via the heat-radiating plate 7, and heat dissipation is conducted efficiently.Type: GrantFiled: September 2, 1999Date of Patent: March 30, 2004Assignee: Texas Instruments IncorporatedInventors: Norito Umehara, Masazumi Amagai
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Patent number: 6713881Abstract: Object: To provide sufficient connection strength between the bonding pads and conductor wires in a wire bonding method. Means for Solution: The bonding pads 20 upon a semiconductor chip 18 are provided with a bonding region 30 and a probe contact region 32, and one end of the conductor wire 22 is bonded to the bonding region 30. The probe contact to the probe contact region 32 is used for making contact to the tips of the test probes in the semiconductor chip inspection step performed prior to the bonding.Type: GrantFiled: May 25, 2001Date of Patent: March 30, 2004Assignee: Texas Instruments IncorporatedInventors: Norito Umehara, Yoshikatsu Umeda
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Publication number: 20020158331Abstract: The invention is to improve the heat radiation of an LOC type semiconductor device. The semiconductor device related to the present invention has a preferably metal heat-radiating element 7 that is in thermal contact with the surface opposite the principal surface of the semiconductor chip 3. One region of said heat-radiating element 7 is externally exposed from the package that encloses the semiconductor chip 3. The above-mentioned heat-radiating element 7 is in thermal contact with a metal pattern 12 that is formed on the substrate 10 on which the semiconductor device is mounted. The heat from the semiconductor chip is transferred to the mounting substrate 10 side via the heat-radiating plate 7, and heat dissipation is conducted efficiently.Type: ApplicationFiled: April 11, 2002Publication date: October 31, 2002Inventors: Norito Umehara, Masazumi Amagai
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Publication number: 20020125584Abstract: Object: To provide sufficient connection strength between the bonding pads and conductor wires in a wire bonding method.Type: ApplicationFiled: May 25, 2001Publication date: September 12, 2002Inventors: Norito Umehara, Yoshikatsu Umeda
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Patent number: 6380634Abstract: The purpose of this invention is to provide a type of conductor wires which are appropriate for making a thin semiconductor device and can minimize problems of short-circuits between wires. This invention pertains to a type of conductor wires for electrically connecting a semiconductor chip to external conductors. According to this invention, each of conductor wires (5) has first end portion (5a) bonded to electrode pad (2) of semiconductor chip (1), second end portion (5b) bonded to external conductor (4), and bending point (A1) which is positioned between the aforementioned first and second end portions and is bent almost in the direction opposite to the direction that the conductor wire rises at the aforementioned first end portion.Type: GrantFiled: July 23, 1999Date of Patent: April 30, 2002Assignee: Texas Instruments IncorporatedInventor: Norito Umehara
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Patent number: 6268644Abstract: To prevent the contact of adjacent wires when a molding resin for forming the external shape of a semiconductor package is poured. The semiconductor device of the present invention is equipped with a semiconductor chip 13 that has a row of electrode pads 13a along the periphery of the principal plane, wires 14 that extend from each of the electrode pads 13a, a molding resin package material 15 that covers at least the above-mentioned semiconductor chip 13 and the wires 14 and that forms the external shape of the semiconductor device, and dam members that are arranged between the two closest of the above-mentioned wires 14a and 14b, which are arranged so that the corners of the above-mentioned semiconductor chip are inserted in between the wires, that is, the dummy wires 17.Type: GrantFiled: August 3, 1999Date of Patent: July 31, 2001Assignee: Texas Instruments IncorporatedInventors: Norito Umehara, Takahiro Imura, Yoshikatsu Umeda
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Patent number: 6225703Abstract: The purpose of the present invention is to reduce the warpage of the semiconductor package caused by thermal contraction. According to the present invention, semiconductor device (9) has plate-shaped member (7) which is positioned on a surface of semiconductor chip (1) and is sealed together with semiconductor chip (1) with molding resin (8). Said plate-shaped member (7) has a linear expansion coefficient that is less than the linear expansion coefficient of the aforementioned molding resin. By placing a plate-shaped member with a small linear expansion coefficient on semiconductor chip (1), it is possible to reduce the thermal contraction on the upper side of the semiconductor chip. Also, the presence of the plate-shaped member on the semiconductor chip leads to substantial reduction in the thickness of the molding resin on the semiconductor chip. The pulling force due to contraction of the molding resin that leads to warping is proportional to the thickness of the molding resin.Type: GrantFiled: July 9, 1999Date of Patent: May 1, 2001Assignee: Texas Instruments IncorporatedInventors: Norito Umehara, Chikara Azuma, Akira Karashima
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Patent number: 6118183Abstract: To provide a type of semiconductor device with high resistance to cracks and having fewer manufacturing steps. Semiconductor device 1 has a substrate having insulating base material 2 mainly made of a thermoplastic polyimide resin. When heated to a temperature above the glass transition temperature, the surface of insulating base material 2 made of thermoplastic polyimide resin melts and exhibits the properties of an adhesive. The adhesive layer is preferred for laminating the metal film for forming conductor pattern 3, and it is preferred for fixing semiconductor IC chip 4 to insulating base material 2 made of thermoplastic polyimide resin. When semiconductor IC chip 4 is fixed on insulating base material 2 made of thermoplastic polyimide resin, the two are brought into contact with each other under a prescribed pressure, and the atmospheric temperature is higher than the glass transition temperature for bonding.Type: GrantFiled: December 15, 1997Date of Patent: September 12, 2000Assignee: Texas Instruments IncorporatedInventors: Norito Umehara, Masazumi Amagai
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Patent number: 6007920Abstract: The wafer dicing/bonding sheet of the present invention comprises a soft film, a pressure sensitive adhesive layer formed on the soft film, a processing film for polyimide type resin composed of a heat resistant resin which has been formed on the pressure sensitive adhesive layer and a polyimide adhesive layer formed on the processing film. It is preferred that the processing film be a polyethylene naphthalate film whose surface has been subjected to an alkyd release treatment. The present invention facilitates expansion to be conducted after the wafer dicing.Type: GrantFiled: June 17, 1998Date of Patent: December 28, 1999Assignees: Texas Instruments Japan, Ltd., Lintec CorporationInventors: Norito Umehara, Masazumi Amagai, Mamoru Kobayashi, Kazuyoshi Ebe
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Patent number: 5960260Abstract: Our semiconductor device is an IC chip 10 whose back surface is affixed to a mounting section 81 by means of a thermoplastic adhesive (for example, thermoplastic polyimide) 84. Package cracks are eliminated or markedly reduced and the problems with productivity for mounting curing and mounting alleviated. Even when a padless special lead frame or one with a small die pad is used, package cracks are eliminated or markedly reduced, and the lead frame can be mounted easily and with good reliability on top of the lead frame.Type: GrantFiled: April 7, 1997Date of Patent: September 28, 1999Assignee: Texas Instruments IncorporatedInventors: Norito Umehara, Masazumi Amagai
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Patent number: 5920116Abstract: In semiconductor device fabrication, warping of the support pins must be prevented so that the semiconductor element can be properly positioned during the wire-bonding and resin-sealing processes. The invention provides a process in which a V-shaped groove 33, for example, is formed in the mounting pad 31 and the support pins 32, imparting rigidity to the support pins 32.Type: GrantFiled: November 27, 1996Date of Patent: July 6, 1999Assignee: Texas Instruments IncorporatedInventors: Norito Umehara, Akira Karashima
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Patent number: 5882956Abstract: A process for manufacturing a wafer dicing/bonding sheet of the present invention comprises a soft film, a pressure sensitive adhesive layer formed on the soft film, a processing film for polyimide type resin composed of a heat resistant resin which has been formed on the pressure sensitive adhesive layer and a polyimide adhesive layer formed on the processing film. It is preferred that the processing film be a polyethylene naphthalate film whose surface has been subjected to an alkyd release treatment. The present invention facilitates expansion to be conducted after the wafer dicing.Type: GrantFiled: January 21, 1997Date of Patent: March 16, 1999Assignees: Texas Instruments Japan Ltd., Lintec CorporationInventors: Norito Umehara, Masazumi Amagai, Mamoru Kobayashi, Kazuyoshi Ebe
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Patent number: 5623123Abstract: Semiconductor device package 53 having a lead frame with a mounting pad 31 smaller than the IC chip 10 mounted thereon, and a method of making a semiconductor device package based on wire bonding using a heater insert 38 with a mounting pad insertion concave part 51. Separation between the mounting pad and an encapsulating resin is eliminated, cracks are not created in the resin, or are considerably reduced, and warpage of the package can be prevented. Also, bonding of wires between leads and respective bonding pads 17 on the chip 10can be executed stably and efficiently.Type: GrantFiled: June 10, 1994Date of Patent: April 22, 1997Assignee: Texas Instruments IncorporatedInventor: Norito Umehara