Abstract: An object is to provide a semiconductor device which is free from such voltage oscillation as may cause malfunction of peripheral equipment. In a semiconductor device having a pin structure, the impurity concentration gradient in an n+ layer (103) serving as a buffer layer is set equal to or less than 2×1018cm−4. Then, when a reverse bias voltage is applied and a depletion layer reaches the n+ layer (103), the expansion of the depletion layer is prevented from rapidly stopping and the voltage oscillation can be suppressed.

Abstract: Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less.

Abstract: A semiconductor device is composed a semiconductor substrate having a first conducting-type first semiconductor layer, a second conducting-type second semiconductor layer, a first conducting-type third semiconductor layer, a second conducting-type fourth semiconductor layer and a first conducting-type fifth semiconductor layer, a first main electrode for short-circuiting the first semiconductor layer and the second semiconductor layer, a second main electrode for short-circuiting the fourth semiconductor layer and the fifth semiconductor layer, and a control electrode provided on the third semiconductor layer. The first semiconductor layer and the second semiconductor layer form a joint. The second semiconductor layer and the third semiconductor layer form a joint. The third semiconductor layer and the fourth semiconductor layer form a joint. The fourth semiconductor layer and the fifth semiconductor layer form a joint.

Abstract: A semiconductor device (102) comprises an N type semiconductor substrate (1). A P layer (22) is formed in a first surface (S1) of the semiconductor substrate (1), and a P layer (23) is formed in the semiconductor substrate (1) and in contact with the first surface (S1) and a second surface (S2) of the semiconductor substrate (1) corresponding to a beveled surface. The P layer (23) surrounds the P layer (22) in non-contacting relationship with the P layer (22). A separation distance (D) between the P layers (22, 23) is set at not greater than 50 &mgr;m. A distance (D23) between a third surface (S3) of the semiconductor substrate (1) and a portion of the P layer (23) which is closer to the third surface (S3) is less than a distance (D22) between the third surface (S3) and a portion of the P layer (22) which is closer to the third surface (S3).

Abstract: The current-limiting device 1 includes a silicon substrate 2 having surfaces opposite to each other, and two electrodes 3 deposited respectively on the opposite surfaces of the silicon substrate. The silicon substrate 2 is of a three-layered structure including an N− layer 4 of a low impurity density and an N+ layers 5 of a high impurity density formed respectively on opposite surfaces of the N− layer 4. The electrodes 3, are deposited on an outer surface of each of the N+ layers 5 remote from the N− layer 4. The constant current substantially flows in the current-limiting device 1 if the applied voltage is higher than a predetermined value.

Abstract: An object is to obtain a semiconductor device having a PN junction which can suppress voltage oscillation without exerting any adverse effects. The film thickness of the N− layer (101) is set to satisfy both of a first condition that the depletion layer extending in the N− layer (101) from the PN junction between the N− layer (101) and the P layer (102) does not reach the N+ layer (103) when a reverse voltage of about ½ to ⅔ of the voltage blocking capability of the diode is applied and a second condition that the depletion layer reaches the N+ layer (103) when a reverse voltage exceeding about ⅔ of the voltage blocking capability is applied. Further, the impurity concentration (specific resistance) of the N− layer (101) is set so that the electric field which acts on the depletion layer when the reverse bias voltage is set equivalent to the voltage blocking capability does not exceed the maximum field strength of silicon.

Abstract: Providing a reverse conducting thyristor, wherein a diode and a GTO thyristor are reverse parallel-connected, with which it is possible to reduce a surface area size of a separation portion and avoid variations in insulation characteristics. A separation portion between a diode and a GTO thyristor includes a semiconductor substrate of a first conductivity type, a thin film region of a second conductivity type formed in a major surface of the semiconductor substrate, and a guard ring region of the second conductivity type.

Abstract: A semiconductor device is composed a semiconductor substrate having a first conducting-type first semiconductor layer, a second conducting-type second semiconductor layer, a first conducting-type third semiconductor layer, a second conducting-type fourth semiconductor layer and a first conducting-type fifth semiconductor layer, a first main electrode for short-circuiting the first semiconductor layer and the second semiconductor layer, a second main electrode for short-circuiting the fourth semiconductor layer and the fifth semiconductor layer, and a control electrode provided on the third semiconductor layer. The first semiconductor layer and the second semiconductor layer form a joint. The second semiconductor layer and the third semiconductor layer form a joint. The third semiconductor layer and the fourth semiconductor layer form a joint. The fourth semiconductor layer and the fifth semiconductor layer form a joint.

Abstract: Providing a reverse conducting thyristor, wherein a diode and a GTO thyristor are reverse parallel-connected, with which it is possible to reduce a surface area size of a separation portion and avoid variations in insulation characteristics.

Abstract: The current-limiting device 1 includes a silicon substrate 2 having surfaces opposite to each other, and two electrodes 3 deposited respectively on the opposite surfaces of the silicon substrate. The silicon substrate 2 is of a three-layered structure including an N− layer 4 of a low impurity density and an N+ layers 5 of a high impurity density formed respectively on opposite surfaces of the N− layer 4. The electrodes 3, are deposited on an outer surface of each of the N+ layers 5 remote from the N− layer 4. The constant current substantially flows in the current-limiting device 1 if the applied voltage is higher than a predetermined value.