Patents by Inventor Noritsugu Nomura
Noritsugu Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11942382Abstract: When a voltage is applied to a semiconductor element formed into a semiconductor substrate for evaluating the electrical characteristic of the semiconductor element, partial discharge between the semiconductor element and an inter-element portion, adhesion of a foreign substance to the semiconductor substrate, and formation of a trace of a component in the semiconductor substrate are prevented. A semiconductor device includes a semiconductor substrate and a discharge inhibitor. The semiconductor substrate includes a plurality of semiconductor elements and an inter-element portion. The semiconductor elements are arranged in a spreading direction of the semiconductor substrate. The inter-element portion is between adjacent semiconductor elements among the semiconductor elements. The discharge inhibitor is bonded not to a surface of a center of each semiconductor element among the semiconductor elements but to a surface of the inter-element portion. The discharge inhibitor is made of an insulator.Type: GrantFiled: May 14, 2020Date of Patent: March 26, 2024Assignee: Mitsubishi Electric CorporationInventor: Noritsugu Nomura
-
Patent number: 11824014Abstract: According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w<Wth, where s is a thickness of the buffer layer, t is a thickness of the electrode, and Wth=2×(s×t?s2)0.5 holds true.Type: GrantFiled: January 21, 2021Date of Patent: November 21, 2023Assignee: Mitsubishi Electric CorporationInventors: Akito Nishii, Tatsuo Harada, Katsumi Uryu, Noritsugu Nomura, Sho Tanaka
-
Publication number: 20230351066Abstract: A method for automatically arranging parts on a CAD comprises: part condition acquisition step A; part arrangement order acquisition step; boundary line acquisition step B; part arrangement step C; boundary line updating step; first repetition step; part type change step; and second repetition step. In step A, part boundary condition, set for each of types of parts, representing the type of the part to be permitted to be arranged adjacent to the part is acquired. In step B, boundary line boundary condition to be set for a boundary line parallel to an area termination end line of an arrangement area in X- or Y-direction is acquired. In step C, the part boundary condition set for the part and the boundary line boundary condition set for the boundary line arranged in the arrangement area are compared with each other, and the part is arranged when the conditions match each other.Type: ApplicationFiled: November 29, 2022Publication date: November 2, 2023Applicant: Mitsubishi Electric CorporationInventors: Katsumi URYU, Koji OKUNO, Noritsugu NOMURA
-
Publication number: 20210305174Abstract: According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w<Wth, where s is a thickness of the buffer layer, t is a thickness of the electrode, and Wth=2×(s×t?s2)0.5 holds true.Type: ApplicationFiled: January 21, 2021Publication date: September 30, 2021Applicant: Mitsubishi Electric CorporationInventors: Akito NISHII, Tatsuo HARADA, Katsumi URYU, Noritsugu NOMURA, Sho TANAKA
-
Publication number: 20210098317Abstract: When a voltage is applied to a semiconductor element formed into a semiconductor substrate for evaluating the electrical characteristic of the semiconductor element, partial discharge between the semiconductor element and an inter-element portion, adhesion of a foreign substance to the semiconductor substrate, and formation of a trace of a component in the semiconductor substrate are prevented. A semiconductor device includes a semiconductor substrate and a discharge inhibitor. The semiconductor substrate includes a plurality of semiconductor elements and an inter-element portion. The semiconductor elements are arranged in a spreading direction of the semiconductor substrate. The inter-element portion is between adjacent semiconductor elements among the semiconductor elements. The discharge inhibitor is bonded not to a surface of a center of each semiconductor element among the semiconductor elements but to a surface of the inter-element portion. The discharge inhibitor is made of an insulator.Type: ApplicationFiled: May 14, 2020Publication date: April 1, 2021Applicant: Mitsubishi Electric CorporationInventor: Noritsugu NOMURA
-
Patent number: 10411093Abstract: An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.Type: GrantFiled: December 28, 2015Date of Patent: September 10, 2019Assignee: Mitsubishi Electric CorporationInventors: Katsumi Nakamura, Tatsuo Harada, Noritsugu Nomura
-
Publication number: 20190109026Abstract: Provided is a technique for detaching a semiconductor chip from a mount tape without failures in the semiconductor chip, such as cracking and chipping. A semiconductor pick-up apparatus includes the following components: a pick-up stage above which a semiconductor chip is to be placed through a mount tape attached to the lower surface of the semiconductor chip; an expander holding and expanding the mount tape; a push-up needle projecting from the upper surface of the pick-up stage, and capable of pushing up the semiconductor chip through the mount tape; and a mechanism pushing up the push-up needle while operating the push-up needle so as to form a spiral shape.Type: ApplicationFiled: August 6, 2018Publication date: April 11, 2019Applicant: Mitsubishi Electric CorporationInventors: Kinya YAMASHITA, Masaki UENO, Tatsuo HARADA, Noritsugu NOMURA
-
Publication number: 20180248003Abstract: An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.Type: ApplicationFiled: December 28, 2015Publication date: August 30, 2018Applicant: Mitsubishi Electric CorporationInventors: Katsumi NAKAMURA, Tatsuo HARADA, Noritsugu NOMURA
-
Publication number: 20140199823Abstract: An SOT substrate (6), in which a silicon layer (5) is provided on a silicon substrate (3) via a silicon oxide film (4), is formed. Next, a plurality of semiconductor elements (8) is formed on a surface of the silicon layer (5). Next, wiring (11) is formed on a surface of an insulating substrate (10). Next, the SOI substrate (6) and the insulating substrate (10) are pasted together so that the plurality of semiconductor elements (8) and the wiring (11) are electrically connected together. Next, at least one of hydrogen ions and rare gas ions are injected into the silicon substrate (3) to form a brittle layer (12). Next, part of the silicon substrate (3) is peeled away from the brittle layer (12) as a boundary.Type: ApplicationFiled: June 10, 2011Publication date: July 17, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Noritsugu Nomura, Akira Okada, Tatsuo Harada
-
Patent number: 8288215Abstract: A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.Type: GrantFiled: March 23, 2011Date of Patent: October 16, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Noritsugu Nomura
-
Publication number: 20110171791Abstract: A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.Type: ApplicationFiled: March 23, 2011Publication date: July 14, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto OHNUMA, Noritsugu NOMURA
-
Patent number: 7939389Abstract: A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.Type: GrantFiled: April 9, 2009Date of Patent: May 10, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Noritsugu Nomura
-
Publication number: 20090263942Abstract: A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.Type: ApplicationFiled: April 9, 2009Publication date: October 22, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto OHNUMA, Noritsugu NOMURA