Abstract: A compile technique is provided for multicore allocation, by which a desired running performance can be achieved. The steps of analyzing a taskization directive, taskizing a specified part, and assigning a specified CPU the task are adopted for the compile technique. According to the program-to-tasks-decomposition compile technique, the multicore decomposition is performed by allocating tasks to CPUs individually while following a task decomposition directive of a main part designated by a user. When no direction is issued concerning a CPU to be allocated, the relation with a principal task is judged from the relation of invocation and the dependency, and CPU to be allocated, and then the CPU to be allocated is determined. In allocation to the CPU, an efficient multicore-task decomposition is achieved in consideration of copy and assignment of one processing to more than one CPU while figuring in the balance between processing speed and resources.

Abstract: In a processor system including a plurality of hardware resources, a method for arranging a program to suppress the power consumption by the resources includes the steps of determining which ones of the hardware resources are to be operated and from which instruction cycle to which instruction cycle to execute each instruction of the program; and based on the determination, adding an instruction to lower frequencies of clock signals inputted to the hardware resources and an instruction to restore the frequency at positions adjacent to the beginning and the end of the period during which the hardware resources are not operated and compiling the program. The processor system decodes the compiled program and lowers the frequency of the clock signal inputted to the hardware resources in accordance with the frequency lowering instruction and the frequency restoring instruction detected in the decoding step.

Abstract: In an information processing system having an instruction buffer, an instruction buffer is controlled to primarily increase the instruction hit ratio of a sequence of instructions including a procedure-call instruction. In the first configuration, there is provided a mechanism which subdivides the instruction buffer into a plurality of instruction buffer banks so as to switch the instruction buffer bank to a current use in association with a dynamic procedure call, thereby improving the instruction hit ratio in the procedure call and in the return operation. In the second configuration, there are provided instruction words to subdivide and to control the instruction buffer such that the user can specify a method of controlling the instruction buffer. An instruction loop is captured efficiently and an arbitrary instruction sequence of a program is stored as a resident routine in the buffer so as to increase the instruction hit ratio.