Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.

Abstract: An adaptive equalizer includes a finite impulse response filter with a predetermined number of taps; and a tap coefficient adaptive controller having a register to hold tap coefficients for the filter, a weighted center calculator to calculate a weighted center of the tap coefficients, and a tap coefficient shifter to shift the tap coefficients based on a calculation result of the weighted center. During an initial training period, the tap coefficient shifter shifts the tap coefficients on a symbol data basis such that a difference between the calculated weighted center of the tap coefficients and a tap center defined by the number of taps is minimized.

Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.

Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.

Abstract: An ALC processing unit to adjust the signal level of outputs from an adaptive equalizer to a target value is provided in a stage later than the adaptive equalizer and earlier than a frequency offset estimation/compensation unit in an optical digital coherent receiver. The ALC processing unit generates a histogram that counts the number of samples for discrete monitored values corresponding to amplitude values of outputs from the adaptive equalizer, and determines a level adjustment coefficient that is to be multiplied by an output from the adaptive equalizer so as to multiply the determined coefficient by the output from the adaptive equalizer so that the monitored value of the peak value of the histogram is the target value.

Abstract: An event-driven simulation is performed on an operation of data transmission from a source hardware element to a destination hardware element. Upon receiving a first request for transmitting first data at a first time-point, data stored in a storage area of the destination hardware element is saved as backup data in a memory, and the first data is stored in the storage area. A first time-period for transmitting the first data is measured from the first time-point. When a second request having a higher priority than the first request is received at a second time-point, a portion of the backup data is restored to the storage area so that the storage area stores third data estimated to have been transmitted to the destination hardware element. After a second time-period for the second request is measured, the first data is again stored in the storage area.

Abstract: A simulation method includes obtaining an execution log generated while a predetermined processing is executed by simulating a series of operations in a test model that is a modeled version of a test target device by causing a predetermined processing to be executed in the test model, extracting a processing unit log constituted by a predetermined processing unit from the execution log obtained in the obtaining, and simulating an operation in which processing corresponding to the processing unit log extracted in the extracting is executed in a test model in which a part of function of the test target device is modified, the operation being simulated on the basis of a setting condition set by a user.

Abstract: The present invention relates to a technique for executing performance evaluation simulation of a system to be implemented by software or hardware. A simulation apparatus includes a first acquisition section for executing existing tentative software to acquire a first execution log, a division section for dividing the first execution log into a plurality of basic processing units, a basic processing execution log production section for modifying some of the plural basic processing units to produce a basic processing execution log to be used for simulation, and a simulation execution section for inputting the basic processing execution log to a hardware model to execute the simulation to acquire information required for the performance evaluation.

Abstract: A redundant logic circuit detection method includes storing unit-logic-circuit information, waveform data and a limiting condition in a storage section. The unit-logic-circuit information indicates a plurality of unit-logic-circuits synthesized based on logic design information. The waveform data indicates a logic simulation result with respect to the plurality of unit-logic-circuits. The limiting condition defines a comparison condition of the waveform data. The method selects a first unit-logic-circuit from the plurality of unit-logic-circuits. The method detects a second unit-logic-circuit having a substantially identical sequence of the waveform data to the first unit-logic-circuit based on the limiting condition. The method outputs the first unit-logic-circuit and the second unit-logic-circuit as redundant circuit information.

Abstract: A performance evaluation simulation apparatus divides a process into basic process units based on an execution log, calculates a throughput of each basic process unit from information held in the execution log, changes an arrangement structure so that a basic process unit with the calculated throughput exceeding a predetermined threshold is disposed in a hardware model, and performs a performance evaluation simulation on the hardware model and a software model to generate statistical information on which performance evaluation is based.

Abstract: An adaptive equalizer includes a finite impulse response filter with a predetermined number of taps; and a tap coefficient adaptive controller having a register to hold tap coefficients for the filter, a weighted center calculator to calculate a weighted center of the tap coefficients, and a tap coefficient shifter to shift the tap coefficients based on a calculation result of the weighted center. During an initial training period, the tap coefficient shifter shifts the tap coefficients on a symbol data basis such that a difference between the calculated weighted center of the tap coefficients and a tap center defined by the number of taps is minimized.

Abstract: An ALC processing unit to adjust the signal level of outputs from an adaptive equalizer to a target value is provided in a stage later than the adaptive equalizer and earlier than a frequency offset estimation/compensation unit in an optical digital coherent receiver. The ALC processing unit generates a histogram that counts the number of samples for discrete monitored values corresponding to amplitude values of outputs from the adaptive equalizer, and determines a level adjustment coefficient that is to be multiplied by an output from the adaptive equalizer so as to multiply the determined coefficient by the output from the adaptive equalizer so that the monitored value of the peak value of the histogram is the target value.

Abstract: A redundant logic circuit detection method includes storing unit-logic-circuit information, waveform data and a limiting condition in a storage section. The unit-logic-circuit information indicates a plurality of unit-logic-circuits synthesized based on logic design information. The waveform data indicates a logic simulation result with respect to the plurality of unit-logic-circuits. The limiting condition defines a comparison condition of the waveform data. The method selects a first unit-logic-circuit from the plurality of unit-logic-circuits. The method detects a second unit-logic-circuit having a substantially identical sequence of the waveform data to the first unit-logic-circuit based on the limiting condition. The method outputs the first unit-logic-circuit and the second unit-logic-circuit as redundant circuit information.

Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.

Abstract: A simulation method includes obtaining an execution log generated while a predetermined processing is executed by simulating a series of operations in a test model that is a modeled version of a test target device by causing a predetermined processing to be executed in the test model, extracting a processing unit log constituted by a predetermined processing unit from the execution log obtained in the obtaining, and simulating an operation in which processing corresponding to the processing unit log extracted in the extracting is executed in a test model in which a part of function of the test target device is modified, the operation being simulated on the basis of a setting condition set by a user.

Abstract: The present invention relates to a technique for executing performance evaluation simulation of a system to be implemented by software or hardware. A simulation apparatus includes a first acquisition section for executing existing tentative software to acquire a first execution log, a division section for dividing the first execution log into a plurality of basic processing units, a basic processing execution log production section for modifying some of the plural basic processing units to produce a basic processing execution log to be used for simulation, and a simulation execution section for inputting the basic processing execution log to a hardware model to execute the simulation to acquire information required for the performance evaluation.

Abstract: A performance evaluation simulation apparatus divides a process into basic process units based on an execution log, calculates a throughput of each basic process unit from information held in the execution log, changes an arrangement structure so that a basic process unit with the calculated throughput exceeding a predetermined threshold is disposed in a hardware model, and performs a performance evaluation simulation on the hardware model and a software model to generate statistical information on which performance evaluation is based.

Abstract: An electronic unit includes a flexible printed circuit board that is mounted with plural electronic components, and forms a layered structure through folding, and a joint that electrically connects wiring parts on two end surfaces of the flexible printed circuit board, at least two of the plural electronic components being connected so that the at least two can communicate with each other through the wiring parts of the joint.

Abstract: A design support apparatus is provided with a first managing part to manage design documents that become input information to design processes, an extracting part to extract at least one of specification undetermined items, inspecting items of results and caution items for design, from the design documents managed by the first managing part, and a display part to display a list of items extracted by the extracting part.

Abstract: A workflow management apparatus that manages a plurality of processes constituting a workflow, comprises: an I/O information acquisition unit 13 that acquires I/O information defining, in each of the processes, output data obtained as a processing result and input data serving as the data related to processing; a process management unit 14 that allows each of the processes to perform processing based on input data of a currently acquired version number; a version number acquisition unit 15 that acquires information related to version numbers of the input and output data handled in each of the processes; and a state registration unit 11 that registers the state of each of the processes, wherein when the output data in any of the processes is updated, the state registration unit resisters the state of the process including the updated output data in the input data thereof as “Being executed” based on the information related to the acquired I/O information and version number.