Patents by Inventor Noriyoshi Ito

Noriyoshi Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190344667
    Abstract: In an outboard motor, a controller controls an electric motor. An output outputs a predetermined notification information in response to a notification command signal output from the controller. When the controller receives a shut-off signal indicating that a semiconductor fuse is off, the controller outputs the notification command signal and causes the output to output notification information. When the controller receives a recovery operation signal indicating a predetermined operation performed by a user from an operator in a state where the semiconductor fuse has turned off, the controller outputs a recovery command signal to the semiconductor fuse.
    Type: Application
    Filed: November 20, 2018
    Publication date: November 14, 2019
    Inventors: Takeshi NAITO, Yoshihiro MIZUSHIMA, Makoto MIZUTANI, Noriyoshi ICHIKAWA, Makoto ITO
  • Patent number: 10366949
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 30, 2019
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Jun Furuichi, Akio Rokugawa, Takashi Ito
  • Patent number: 9612595
    Abstract: A chatter vibration suppressing method includes acquiring a moment of inertia of a rotating body, recording a value indicating the acquired moment of inertia into a machining program, and calculating a variable amplitude and a variable period when a rotation speed of the rotating body is varied in order to suppress chatter vibration from the value indicating the moment of inertia recorded in the machining program and the maximum input power of a motor for rotating the rotating body.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: April 4, 2017
    Assignee: OKUMA CORPORATION
    Inventors: Kiyoshi Yoshino, Yuto Mizukami, Takayuki Kato, Noriyoshi Ito, Nobuki Nishidera
  • Patent number: 9039588
    Abstract: In a combination machining lathe, a workpiece holding device holds a workpiece in a manner that permits the workpiece to rotate around an axis parallel to a direction of a horizontal Z axis. A tool post holds a tool that comprises a holder and a bit. The tool held by the tool post is indexed to a position in which the longitudinal axis of the holder is parallel to an X axis direction. The bit of the tool held by the tool post is angled such that a longitudinal axis of the bit is disposed in a position tilted away from the X axis direction closer to a horizontal axis in a plane containing the X axis and the Y axis. A turning operation is performed while the tool and/or the workpiece are moved relative to each other in a direction of the longitudinal axis of the bit.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: May 26, 2015
    Assignee: Okuma Corporation
    Inventors: Takaharu Ito, Kouta Ashiuchi, Norio Kamegai, Noriyoshi Ito, Takuya Kato
  • Publication number: 20140114462
    Abstract: A chatter vibration suppressing method includes acquiring a moment of inertia of a rotating body, recording a value indicating the acquired moment of inertia into a machining program, and calculating a variable amplitude and a variable period when a rotation speed of the rotating body is varied in order to suppress chatter vibration from the value indicating the moment of inertia recorded in the machining program and the maximum input power of a motor for rotating the rotating body.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 24, 2014
    Applicant: OKUMA Corporation
    Inventors: Kiyoshi Yoshino, Yuto Mizukami, Takayuki Kato, Noriyoshi Ito, Nobuki Nishidera
  • Patent number: 7957950
    Abstract: A hard/soft cooperative verifying simulator is based on a SystemC simulator, and provides the capability of reducing overhead of context switching control thereby to shorten processing time. Time keepers for controlling simulation times of a plurality of threads are provided corresponding to the threads generated as simulation models for hardware and software. Each of the time keepers has a variable which holds a simulation time for each thread, a variable which holds a summation time, and a break request queue which stores a break time and its corresponding break method therein. The time keeper manages both variables and the queue in response to six types of method invocations from the thread, and invokes a wait function of the SystemC simulator when necessary. It is thus possible to reduce the number of times that a wait function invocation is performed, and shorten the entire processing time.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: June 7, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Noriyoshi Ito
  • Publication number: 20100101383
    Abstract: In a combination machining lathe, a workpiece holding device holds a workpiece in a manner that permits the workpiece to rotate around an axis parallel to a direction of a horizontal Z axis. A tool post holds a tool that comprises a holder and a bit. The tool held by the tool post is indexed to a position in which the longitudinal axis of the holder is parallel to an X axis direction. The bit of the tool held by the tool post is angled such that a longitudinal axis of the bit is disposed in a position tilted away from the X axis direction closer to a horizontal axis in a plane containing the X axis and the Y axis. A turning operation is performed while the tool and/or the workpiece are moved relative to each other in a direction of the longitudinal axis of the bit.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 29, 2010
    Applicant: OKUMA CORPORATION
    Inventors: Takaharu Ito, Kouta Ashiuchi, Norio Kamegai, Noriyoshi Ito, STakuya Kato
  • Publication number: 20090222250
    Abstract: The present invention provides a hard/soft cooperative verifying simulator based on a SystemC simulator, capable of reducing overhead of context switching control thereby to shorten processing time. Time keepers for controlling simulation times of a plurality of threads are provided corresponding to the threads generated as simulation models for hardware and software. Each of the time keepers has a variable which holds a simulation time for each thread, a variable which holds a summation time, and a break request queue which stores a break time and its corresponding break method therein. The time keeper manages both variables and the queue in response to six types of method invocations from the thread, and invokes a wait function of the SystemC simulator when necessary. It is thus possible to reduce the number of times that a wait function invocation is performed, and shorten the entire processing time.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Noriyoshi ITO
  • Patent number: 7558355
    Abstract: A predetermined syncword detecting circuit includes a matched-bit-number comparing circuit, a comparing-result-change detecting circuit, a detected-result storing circuit, a total number detecting circuit, and a syncword detecting circuit. The matched-bit-number comparing circuit acquires and compares a number of bits in a baseband signal that matches bits of the predetermined syncword with a threshold. The comparing-result-change detecting circuit samples the comparison result, and detects changes in the comparison result. The detected-result storing circuit sequentially stores a result of the comparing-result-change detecting circuit. The total-number detecting circuit detects a total number of the result of the matched-bit-number comparing circuit. The result is included in an N cycle period and surpasses the threshold. The syncword detecting circuit detects the predetermined syncword and selects an intermediate phase of the cycles as a detection phase.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: July 7, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Noriyoshi Ito
  • Publication number: 20090121430
    Abstract: To provide a card for a dice game capable of simply and conveniently enjoying a game substantially similar to a bingo game by using a dice in place of a numeral lottery machine, there is provided a card used in a dice game of a bingo game type using a dice, in which a surface of the card is provided with vertical 4 columns and horizontal 4 rows of boxes, and numerals indicating sums of numerals of pips on dices and pairs of equal numerals which come out when two pieces of dices are cast once or one piece of a dice is cast twice are described in the boxes.
    Type: Application
    Filed: May 8, 2008
    Publication date: May 14, 2009
    Inventor: Noriyoshi Ito
  • Patent number: 7151812
    Abstract: A sample clock extracting circuit comprises including a number-of-change point memory, a number-of-change point updating circuit and an output clock phase determining circuit. The number-of-change point memory stores a number-of-change-point information set every N types of clock phases each having a frequency equivalent to N times a symbol transmission rate of an input baseband signal. The number-of-change point updating circuit updates the number-of-change point information stored in the number-of-change point memory about a clock phase related to timing thereof when a rising change point or a falling change point occurs in the baseband signal. The output clock phase determining circuit determines a clock phase directly or indirectly indicative of a sample clock phase for the baseband signal based on the number-of-change-point information stored in the number-of-change point memory.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: December 19, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Noriyoshi Ito
  • Patent number: 7120851
    Abstract: The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: October 10, 2006
    Assignee: Oki Techno Centre (Singapore) PTE LTD
    Inventors: Yu Jing Ting, Noriyoshi Ito, Hiroshi Katsuragawa
  • Publication number: 20050163274
    Abstract: A predetermined syncword detecting circuit includes a matched-bit-number comparing circuit, a comparing-result-change detecting circuit, a detected-result storing circuit, a total number detecting circuit, and a syncword detecting circuit. The matched-bit-number comparing circuit acquires a number of bits in a baseband signal that matches bits of the predetermined syncword and compares the number with a first threshold. The comparing-result-change detecting circuit samples the result of the matched-bit-number comparing circuit. The comparing-result-change detecting circuit detects changes in the result of the matched-bit-number comparing circuit. The detected-result storing circuit sequentially stores a result of the comparing-result-change detecting circuit. The total-number detecting circuit detects a total number of the result of the matched-bit-number comparing circuit. The result is included in an N cycle period and surpasses the first threshold.
    Type: Application
    Filed: December 15, 2004
    Publication date: July 28, 2005
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Noriyoshi Ito
  • Publication number: 20040083252
    Abstract: The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.
    Type: Application
    Filed: August 28, 2003
    Publication date: April 29, 2004
    Applicant: Oki Techno Centre (Singapore) Pte Ltd.
    Inventors: Yu Jing Ting, Noriyoshi Ito, Hiroshi Katsuragawa
  • Publication number: 20040004935
    Abstract: The present invention relates to methods and devices for receiving signals in a Wireless Local Area Network (wireless LAN, or WLAN), particularly in the case that the signals are Orthogonal Frequency Division Multiplexed (OFDM) signals. A frequency tracking apparatus for an OFDM receiver is disclsoed having means for determining the correlation of corresponding samples of two received pilot carrier symbols, one said sample delayed a predetermined duration with respect to the other; means for integrating said correlation over an integration window and means for determining a frequency tracking error from the sum of said integration.
    Type: Application
    Filed: March 27, 2003
    Publication date: January 8, 2004
    Applicant: Oki Techno Centre (Singapore) Pte Ltd.
    Inventors: Junjie Zhu, Noriyoshi Ito
  • Publication number: 20040004933
    Abstract: The present invention relates to methods and devices for receiving signals in a Wireless Local Area Network (wireless LAN, or WLAN), particularly in the case that the signals are Orthogonal Frequency Division Multiplexed (OFDM) signals. An Automatic Gain Control apparatus for an OFDM receiver is disclosed, having means for determining the average power of received preamble symbols in order to set an appropriate AGC level, means for determining a first AGC level based on the average power of a first number of symbols and means for determining a second AGC level based on the average power of a second number of subsequent symbols.
    Type: Application
    Filed: March 27, 2003
    Publication date: January 8, 2004
    Applicant: Oki Techno Centre (Singapore) Pte Ltd, a company organized and existing under the laws of singapore
    Inventors: Junjie Zhu, Noriyoshi Ito
  • Publication number: 20040005018
    Abstract: The present invention relates to methods and devices for receiving signals in a Wireless Local Area Network (wireless LAN, or WLAN), particularly in the case that the signals are Orthogonal Frequency Division Multiplexed (OFDM) signals. A signal detection apparatus is disclosed for an OFDM receiver, having: means for determining the correlation of corresponding samples of two received preamble symbol samples, one said sample delayed a predetermined duration with respect to the other; signal detection being indicated when the correlation is greater than or equal to a threshold; wherein the threshold is dependent on the signal power of the received preamble symbols.
    Type: Application
    Filed: March 27, 2003
    Publication date: January 8, 2004
    Applicant: Oki Techno Centre (Singapore) Pte Ltd
    Inventors: Junjie Zhu, Noriyoshi Ito
  • Publication number: 20040005022
    Abstract: The present invention relates to methods and devices for receiving signals in a Wireless Local Area Network (wireless LAN, or WLAN), particularly in the case that the signals are Orthogonal Frequency Division Multiplexed (OFDM) signals. A symbol timing apparatus for an OFDM receiver is disclosed having: means for determining the correlation of corresponding samples of two received preamble symbols, one said sample delayed a predetermined duration with respect to the other; means for determining the maximum correlation value within a predetermined integration window, said maximum value indicating the start of a symbol; wherein the integration window duration is not equal to said delay duration.
    Type: Application
    Filed: March 27, 2003
    Publication date: January 8, 2004
    Applicant: Oki Techno Centre (Singapore) Pte Ltd.
    Inventors: Junjie Zhu, Noriyoshi Ito
  • Publication number: 20040004934
    Abstract: The present invention relates to methods and devices for receiving signals in a Wireless Local Area Network (wireless LAN, or WLAN), particularly in the case that the signals are Orthogonal Frequency Division Multiplexed (OFDM) signals. A frequency offset estimation apparatus for an OFDM receiver is disclosed, having: means for determining a first frequency offset having means for determining the correlation of corresponding samples of two received preamble symbol samples a first predetermined delay duration apart; means for determining a second frequency offset having means for determining the correlation of corresponding samples of two received preamble symbol samples a second predetermined delay duration apart, said second delay duration being different from said first delay duration; and means for combining said first and second frequency offsets in order to determine said frequency offset estimation.
    Type: Application
    Filed: March 27, 2003
    Publication date: January 8, 2004
    Applicant: Oki Techno Centre (Singapore) Pte Ltd
    Inventors: Junjie Zhu, Noriyoshi Ito
  • Patent number: D595786
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: July 7, 2009
    Inventor: Noriyoshi Ito