Patents by Inventor Noriyoshi Tozawa

Noriyoshi Tozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device with an improved erroneous write characteristic and erasure characteristic
    Patent number: 5252846
    Abstract: A semiconductor memory device containing a number of memory cells each having a floating gate, an erase gate, and a control gate. In a data erasure mode, electrons are discharged from the floating gate into the erase gate. In the semiconductor memory device, an impurity concentration in at least a region of the floating gate overlapping with the erase gate is lower than that of the erase gate.
    Type: Grant
    Filed: July 7, 1992
    Date of Patent: October 12, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Tanaka, Masayuki Hori, Kazunori Kanebako, Noriyoshi Tozawa
  • Low-melting point glass sealed semiconductor device and method of manufacturing the same
    Patent number: 5237206
    Abstract: A low-melting point glass sealed semiconductor device comprises a pair of ceramic substrates, each of which is shaped like an arch. The ceramic substrates are overlaid with each other, in such a manner as to define a space between them. Through this space, a gas generated from a thermosetting mounting agent used for adhesion is guided to the outside of the semiconductor device.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: August 17, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamitsu Yahata, Noriyoshi Tozawa, Toshiki Tsushima
  • Semiconductor memory device
    Patent number: 4996572
    Abstract: A semiconductor memory device containing a number of memory cells each having a floating gate, an erase gate, and a control gate. In a data erasure mode, electrons are discharged from the floating gate into the erase gate electrode. An insulating film interlaid between the erase gate and the control gate has a three-layered structure consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
    Type: Grant
    Filed: December 11, 1989
    Date of Patent: February 26, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Tanaka, Masayuki Hori, Noriyoshi Tozawa