Patents by Inventor Noriyuki ASAMI

Noriyuki ASAMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11264215
    Abstract: A semiconductor manufacturing apparatus includes: a stage configured to support a semiconductor substrate; and a conductive annular member provided at an outer circumferential portion of the stage and configured to enclose the semiconductor substrate when supported on the stage. The stage has a groove that is provided below a lower portion of an inner circumferential end of the annular member.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 1, 2022
    Assignee: Kioxia Corporation
    Inventors: Toshiaki Asai, Noriyuki Asami
  • Publication number: 20200273679
    Abstract: A semiconductor manufacturing apparatus includes: a stage configured to support a semiconductor substrate; and a conductive annular member provided at an outer circumferential portion of the stage and configured to enclose the semiconductor substrate when supported on the stage. The stage has a groove that is provided below a lower portion of an inner circumferential end of the annular member.
    Type: Application
    Filed: August 30, 2019
    Publication date: August 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Toshiaki ASAI, Noriyuki ASAMI
  • Publication number: 20170069655
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device is disclosed. A trench is formed in a structure on a body. The structure includes first and second films alternately stacked in a first direction. A part of the first films is removed through the trench. One of the first films has a first side surface. Other one of the first films having a second side surface is positioned between the one of the first films and the body. The removing makes a distance between the trench and the second side surface shorter than a distance between the trench and the first side surface. A first space formed by the removing is filled with an insulating material. The first films are removed via a hole formed in the structure. A second space formed by the removing the first films is filled with a conductive material.
    Type: Application
    Filed: February 8, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daigo ICHINOSE, Junichi HASHIMOTO, Noriyuki ASAMI
  • Publication number: 20160172210
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a wafer setting module including an upper face provided with one or more openings, a wafer being to be set on the upper face. The apparatus further includes a first particle supply module configured to supply first particles from the openings to an end portion of the wafer set on the wafer setting module to remove a film formed on the end portion of the wafer by using the first particles.
    Type: Application
    Filed: March 11, 2015
    Publication date: June 16, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Noriyuki ASAMI
  • Patent number: 9082783
    Abstract: The semiconductor device fabrication method of the present invention includes: laminating a plurality of amorphous silicon films on a semiconductor substrate, forming through-holes that pass through the plurality of amorphous silicon films, and subjecting the plurality of amorphous silicon films 301 that include the through-holes to an etching process that uses an alkaline aqueous solution; wherein the plurality of amorphous silicon films is formed to include a first amorphous silicon film and a second amorphous silicon film in which the rate of etching by using the alkaline aqueous solution is slower than that of the first amorphous silicon film and the first amorphous silicon film is interposed between the semiconductor substrate and the second amorphous silicon film.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: July 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Yamawaki, Noriyuki Asami, Shigehisa Inoue
  • Publication number: 20150079756
    Abstract: The semiconductor device fabrication method of the present invention includes: laminating a plurality of amorphous silicon films on a semiconductor substrate, forming through-holes that pass through the plurality of amorphous silicon films, and subjecting the plurality of amorphous silicon films 301 that include the through-holes to an etching process that uses an alkaline aqueous solution; wherein the plurality of amorphous silicon films is formed to include a first amorphous silicon film and a second amorphous silicon film in which the rate of etching by using the alkaline aqueous solution is slower than that of the first amorphous silicon film and the first amorphous silicon film is interposed between the semiconductor substrate and the second amorphous silicon film.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 19, 2015
    Inventors: Hiroki YAMAWAKI, Noriyuki ASAMI, Shigehisa INOUE
  • Publication number: 20140202946
    Abstract: The piping joint according to the present embodiment includes a joint part that joins a plurality of pipes for transporting a medium to one another. At least one conductive line is provided between the pipes so as to extend over cross-sections of the pipes. A ground part grounds the conductive line. The conductive line removes electric charges from the medium via the ground part.
    Type: Application
    Filed: May 21, 2013
    Publication date: July 24, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noriyuki ASAMI, Koudai KITAMURA, Katsuhiko TACHIBANA, Kenzo KUGIMIYA, Nobuhide YAMADA