Abstract: A counter includes: a count processing circuit including a nonvolatile register; a regulator receiving voltage from a direct current power supply, generating power supply voltage based on the received voltage for the count processing circuit, and supplying the power supply voltage to the count processing circuit; and a delay circuit receiving the power supply voltage and supplying a count signal to the count processing circuit after the power supply voltage is supplied to the count processing circuit. After having received the power supply voltage from the regulator, the count processing circuit updates a count value in response to the count signal and holds the updated count value in the nonvolatile register in a non-volatile manner.

Abstract: A counter includes: a count processing circuit including a nonvolatile register; a regulator receiving voltage from a direct current power supply, generating power supply voltage based on the received voltage for the count processing circuit, and supplying the power supply voltage to the count processing circuit; and a delay circuit receiving the power supply voltage and supplying a count signal to the count processing circuit after the power supply voltage is supplied to the count processing circuit. After having received the power supply voltage from the regulator, the count processing circuit updates a count value in response to the count signal and holds the updated count value in the nonvolatile register in a non-volatile manner.

Abstract: In a digital audio interface signal demodulating apparatus (DDAp) that adds a preamble (PA) and additional information (V, U, C, P) to a digital audio signal (Sda) and demodulates into a digital audio interface signal (Sdai) after subjected to bi-phase modulation for transmission, based on both of positive and negative edges of a reference clock (Src) having a frequency higher than twice a minimum inverse frequency (1/T) of said digital audio interface signal (Sdai) and not necessarily synchronizing with said digital audio interface signal (Sdai), a modulation period (nT) of the digital audio interface signal (Sdai) is decided, and a decision signal (Sj) is generated. Furthermore, based on the decision signal (Sj), the: preamble (PA) is detected, and based on the detected preamble (PA), an audio signal (Sda) is obtained from said decision signal (Sj) through demodulation.

Abstract: A rotation control apparatus for controlling a rotation of a recording medium in which a signal modulated in a run length limited code has been recorded in concentric or spiral information tracks at a constant linear velocity. An inversion time detecting circuit alternately detects a maximum or minimum transition interval of a reproduced digital signal from its rise transition to its fall transition, and a maximum or minimum transition interval of the reproduced digital signal from its fall transition to its rise transition, so as to thereby produce a transition interval signal corresponding to each of the detected maximum or minimum values. A motor drive circuit drives a motor in such a direction as to reduce a difference between the value of the transition interval signal and a predetermined value.