Patents by Inventor Noriyuki Homma
Noriyuki Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7123534Abstract: A semiconductor memory device in which memory cells are arranged at intersections between the word lines and the bit lines includes a control unit for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line and refreshing memory cells corresponding to the second word line. The memory cell includes an amplifier section including two driver transistors of which gate and drain electrodes are respectively cross-coupled with each other and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit line. Either one of each transistor and each selector transistor is an n-channel transistor or a p-type transistor.Type: GrantFiled: September 20, 2004Date of Patent: October 17, 2006Assignee: Renesas Technology Corp.Inventors: Hiroaki Nambu, Noriyuki Homma
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Publication number: 20050063238Abstract: A semiconductor memory device in which memory cells are arranged at intersections between the word lines and the bit lines includes a control unit for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line and refreshing memory cells corresponding to the second word line. The memory cell includes an amplifier section including two driver transistors of which gate and drain electrodes are respectively cross-coupled with each other and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit line. Either one of each transistor and each selector transistor is an n-channel transistor or a p-type transistor.Type: ApplicationFiled: September 20, 2004Publication date: March 24, 2005Inventors: Hiroaki Nambu, Noriyuki Homma
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Patent number: 6864559Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: March 4, 2003Date of Patent: March 8, 2005Assignee: Renesas Technology Corp.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 6740958Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: April 4, 2002Date of Patent: May 25, 2004Assignee: Renesas Technology Corp.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Publication number: 20030178699Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: ApplicationFiled: March 4, 2003Publication date: September 25, 2003Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Publication number: 20020153591Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: ApplicationFiled: April 4, 2002Publication date: October 24, 2002Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 6208010Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: December 18, 1995Date of Patent: March 27, 2001Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5497023Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: December 8, 1994Date of Patent: March 5, 1996Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikasu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5448527Abstract: A decoder formed of multiple circuit blocks each including bipolar transistors Q1 and Q2 having their collectors connected to resistors R1 and R2, respectively, a bipolar transistor Q3 having its collector supplied with a power voltage, and a current source I1 connected commonly to the emitters of Q1-Q3. This circuit configuration permits the decoder and BiCMOS memories using it to operate with a low supply voltage.Type: GrantFiled: November 10, 1993Date of Patent: September 5, 1995Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroaki Nambu, Noriyuki Homma, Kazuo Kanetani, Youji Idei, Kenichi Ohhata, Takesi Kusunoki
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Patent number: 5398201Abstract: A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished.Type: GrantFiled: April 28, 1993Date of Patent: March 14, 1995Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroaki Nambu, Noriyuki Homma, Kunihiko Yamaguchi, Hisayuki Higuchi, Kazuo Kanetani, Youji Idei, Ken'ichi Ohata, Yoshiaki Sakurai, Masanori Odaka, Goro Kitsukawa
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Patent number: 5386135Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: April 12, 1994Date of Patent: January 31, 1995Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5324982Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: October 2, 1991Date of Patent: June 28, 1994Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5255225Abstract: A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.Type: GrantFiled: March 4, 1992Date of Patent: October 19, 1993Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroaki Nambu, Noriyuki Homma, Kunihiko Yamaguchi, Kazuo Kanetani, Hisayuki Higuchi, Youji Idei, Kenichi Ohata, Yoshiaki Sakurai, Masanori Odaka, Goro Kitsukawa, Nobuo Tamba, Masayuki Ohayashi, Toshiro Hiramoto, Kayoko Saito
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Patent number: 5163022Abstract: The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R >I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.Type: GrantFiled: January 30, 1992Date of Patent: November 10, 1992Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Noriyuki Homma, Hiroaki Nambu, Kunihiko Yamaguchi, Tohru Nakamura, Youji Idei, Kazuo Kanetani, Kenichi Ohhata, Yoshiaki Sakurai, Hisayuki Higuchi
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Patent number: 5148255Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: January 23, 1991Date of Patent: September 15, 1992Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5086414Abstract: A semiconductor circuit having a plurality of circuit blocks, each having latch circuits each one thereof being controlled by an internally provided clock signal for preventing malfunction of the circuit. Each circuit is provided with the latch function so that the cycle time is made shorter than the access time. Moreover, the latch means are driven in such a manner that the adjoining ones are prevented from being put to through-state simultaneously, whereby malfunction is prevented.Type: GrantFiled: November 15, 1989Date of Patent: February 4, 1992Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroaki Nambu, Noriyuki Homma, Kunihiko Yamaguchi, Kazuo Kanetani, Youji Idei, Kenichi Ohhata, Yoshiaki Sakurai, Jun Etoh
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Patent number: 4986666Abstract: A semiconductor memory device capable of operating at high speeds, and a sense circuit and a decoder circuit that can be suitably used for the memory device. A latch function is imparted to at least either one of the decoder circuit or the sense circuit in the semiconductor memory device.Type: GrantFiled: November 29, 1988Date of Patent: January 22, 1991Assignees: Hitachi Device Engineering Co., Ltd., Hitachi Ltd.Inventors: Noriyuki Homma, Hisayuki Higuchi, Yoji Idei, Hiroaki Nambu, Yoshiaki Sakurai
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Patent number: 4958320Abstract: A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.Type: GrantFiled: June 2, 1989Date of Patent: September 18, 1990Assignee: Hitachi, Ltd.Inventors: Noriyuki Homma, Tohru Nakamura, Kazuo Nakazato, Motoaki Matsumoto, Tetsuya Hayashida, Masaharu Kubo, Kazuhiko Sagara
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Patent number: 4942555Abstract: A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line.Type: GrantFiled: July 7, 1989Date of Patent: July 17, 1990Assignee: Hitachi, Ltd.Inventors: Hisayuki Higuchi, Makoto Suzuki, Noriyuki Homma, Kiyoo Itoh
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Patent number: 4937480Abstract: A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance. In still another example, in a CMOS NOR ciruit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.Type: GrantFiled: June 27, 1989Date of Patent: June 26, 1990Assignee: Hitachi, Ltd.Inventors: Hisayuki Higuchi, Makoto Suzuki, Noriyuki Homma