Patents by Inventor Noriyuki Inoue

Noriyuki Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741357
    Abstract: A method of observing a liquid specimen in an electron microscope includes: housing the liquid specimen in a space formed by a specimen stage and a lid member; and observing the liquid specimen, wherein the lid member includes a water retaining material, and a supporting member for supporting the water retaining material, and the water retaining material is provided with a through-hole that enables passage of an electron beam with which the liquid specimen is irradiated.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: August 11, 2020
    Assignee: JEOL Ltd.
    Inventors: Noriyuki Inoue, Toshiaki Suzuki, Yoshiko Takashima
  • Patent number: 10727295
    Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tatsuya Funaki, Noriyuki Inoue
  • Patent number: 10658111
    Abstract: A capacitor having a conductive porous substrate with at least two electrostatic capacitance forming sections, each of the at least two electrostatic capacitance forming sections including a porous portion of the conductive porous substrate, a dielectric layer on the porous portion, and an upper electrode on the dielectric layer. The at least two electrostatic capacitance forming sections are electrically connected in series by the conductive porous substrate.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 19, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Hattori, Noriyuki Inoue, Hiromasa Saeki, Kensuke Aoki, Ken Ito
  • Patent number: 10546691
    Abstract: A capacitor that includes a conductive base material with high specific surface area, a dielectric layer covering the conductive base material with high specific surface area, and an upper electrode covering the dielectric layer, in which the conductive base material with high specific surface area is formed of a metal sintered body as a whole.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noriyuki Inoue, Takeo Arakawa, Kensuke Aoki, Hiromasa Saeki, Koichi Kanryo, Akihiro Tsuru, Haruhiko Mori
  • Publication number: 20190355516
    Abstract: A capacitor is provided that includes an electrostatic capacitance forming portion with a first electrode/dielectric layer/second electrode structure, and a silicon portion. Moreover, the silicon portion is disposed on at least a part of a side of the electrostatic capacitance forming portion. When the capacitor is viewed in a thickness direction thereof, a region occupied by the silicon portion in a lower portion of the electrostatic capacitance forming portion is 50% or less.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventors: Takehito Ishihara, Noriyuki Inoue, Tatsuya Funaki
  • Publication number: 20190295813
    Abstract: A method of observing a liquid specimen in an electron microscope includes: housing the liquid specimen in a space formed by a specimen stage and a lid member; and observing the liquid specimen, wherein the lid member includes a water retaining material, and a supporting member for supporting the water retaining material, and the water retaining material is provided with a through-hole that enables passage of an electron beam with which the liquid specimen is irradiated.
    Type: Application
    Filed: March 25, 2019
    Publication date: September 26, 2019
    Inventors: Noriyuki Inoue, Toshiaki Suzuki, Yoshiko Takashima
  • Patent number: 10256045
    Abstract: A capacitor that includes a porous metal base material, a first buffer layer formed by an atomic layer deposition method on the porous metal base material, a dielectric layer formed by an atomic layer deposition method on the first buffer layer, and an upper electrode formed on the dielectric layer.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiromasa Saeki, Noriyuki Inoue, Takeo Arakawa, Naoki Iwaji
  • Publication number: 20190074347
    Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: March 7, 2019
    Inventors: Tatsuya Funaki, Noriyuki Inoue
  • Patent number: 10204744
    Abstract: A capacitor that includes a porous metallic base material; a phosphorus-containing layer on the porous metallic base material; a dielectric layer on the phosphorus-containing layer; and an electrode on the dielectric layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: February 12, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takeo Arakawa, Hiromasa Saeki, Noriyuki Inoue, Naoki Iwaji
  • Patent number: 10186383
    Abstract: A capacitor that includes a porous metal base material, a dielectric layer formed on the porous metal base material, an upper electrode formed on the dielectric layer, a first terminal electrode electrically connected to the porous metal base material, and a second terminal electrode electrically connected to the upper electrode. The porous metal base material includes a high-porosity part and low-porosity parts, and the low-porosity parts are present at a pair of opposed side surfaces of the porous metal base material.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: January 22, 2019
    Assignee: MURATA MANUFACTURING CO., LTD
    Inventors: Kazuo Hattori, Noriyuki Inoue, Takeo Arakawa, Hiromasa Saeki
  • Publication number: 20180174760
    Abstract: A capacitor includes a first electrode formed from a conductive porous base material, a dielectric layer located on the first electrode and a second electrode located on the dielectric layer. The first electrode is electrically connected to first and second terminal electrodes located on respective opposite ends of the first electrode. The second electrode is located between the first and second terminal electrodes and is electrically connected to a third terminal electrode located on the second electrode.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 21, 2018
    Inventors: KAZUO HATTORI, Noriyuki Inoue
  • Publication number: 20180158610
    Abstract: A capacitor that includes a conductive base material with high specific surface area, a dielectric layer covering the conductive base material with high specific surface area, and an upper electrode covering the dielectric layer, in which the conductive base material with high specific surface area is formed of a metal sintered body as a whole.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 7, 2018
    Inventors: NORIYUKI INOUE, Takeo Arakawa, Kensuke Aoki, Hiromasa Saeki, Koichi Kanryo, Akihiro Tsuru, Haruhiko Mori
  • Publication number: 20180158611
    Abstract: A capacitor that includes a conductive porous base material having a porous portion; a dielectric layer on the porous portion; and an upper electrode on the dielectric layer. In the porous portion of the conductive porous base material, a portion having a base material thickness between pores of 1.2 times or less of a thickness of the dielectric layer exits in 5% or more of the entire porous portion, and the dielectric layer is formed from a compound including atoms having an origin different from an origin of the conductive porous base material.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 7, 2018
    Inventors: Takeo Arakawa, Noriyuki Inoue, Hiromasa Saeki, Naoki Iwaji
  • Publication number: 20180151297
    Abstract: A capacitor having a conductive porous substrate with at least two electrostatic capacitance forming sections, each of the at least two electrostatic capacitance forming sections including a porous portion of the conductive porous substrate, a dielectric layer on the porous portion, and an upper electrode on the dielectric layer. The at least two electrostatic capacitance forming sections are electrically connected in series by the conductive porous substrate.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 31, 2018
    Inventors: KAZUO HATTORI, Noriyuki Inoue, Hiromasa Saeki, Kensuke Aoki, Ken Ito
  • Publication number: 20180132356
    Abstract: A method for manufacturing a capacitor built-in substrate includes: preparing a capacitor built-in core insulating film and laminating a respective buildup layer to each of opposed main surfaces of the capacitor built-in core insulating film. The capacitor built-in core insulating film includes a first and second metal layers, an insulating layer and a capacitor. The first and second metal layers are disposed so as to face each other with the insulating layer interposed therebetween. The capacitor is disposed so as to extend through the insulating layer with one capacitor electrode being electrically connected to the first metal layer and the other capacitor electrode being electrically connected to the second metal layer.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 10, 2018
    Inventors: TATSUYA FUNAKI, Noriyuki Inoue
  • Publication number: 20180114640
    Abstract: A capacitor having an element main body including a metal high specific surface area substrate which has fine pores formed therein and has a large specific surface area; a dielectric layer in a prescribed region on the surface of the high specific surface area substrate including the inner surfaces of the pores; and a conductive part on the dielectric layer. A first terminal electrode is electrically connected to the high specific surface area substrate. A second terminal electrode is electrically connected to the conductive part. The element main body includes a first region that contributes to the acquisition of the capacitance and second regions having a smaller void ratio than the first region. The second regions have a void ratio of 25% or less.
    Type: Application
    Filed: December 21, 2017
    Publication date: April 26, 2018
    Inventors: NORIYUKI INOUE, Kazuo Hattori, Hiromasa Saeki
  • Publication number: 20180114647
    Abstract: A capacitor having an element main body including a metal high specific surface area substrate which has fine pores formed therein and a large specific surface area; a dielectric layer formed in a prescribed region on the surface of the high specific surface area substrate including the inner surfaces of the pores; and a conductive part on the dielectric layer. A first terminal electrode is electrically connected to the high specific surface area substrate. A second terminal electrode is electrically connected to the conductive part. The dielectric layer is interposed between the conductive part and the high specific surface area substrate, and the high specific surface area substrate and the second terminal electrode are electrically insulated from each other.
    Type: Application
    Filed: December 21, 2017
    Publication date: April 26, 2018
    Inventors: Noriyuki Inoue, Kazuo Hattori, Hiromasa Saeki
  • Patent number: 9916963
    Abstract: A specimen loading method for loading a specimen that contains water into a specimen chamber of a charged particle beam device, includes: a step (S100) of mounting the specimen on a specimen support; a step (S102) of covering a predetermined area of the specimen with a water retention material; a step (S104) of evacuating the specimen chamber in which the specimen having the predetermined area covered with the water retention material is placed; and a step (S106) of exposing the predetermined area covered with the water retention material.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 13, 2018
    Assignee: JEOL Ltd.
    Inventors: Noriyuki Inoue, Yoshiko Takashima
  • Publication number: 20180047517
    Abstract: A capacitor that includes a conductive metal base material with a porous part, a dielectric layer on the porous part, and an upper electrode on the dielectric layer, and has an electrostatic capacitance formation part only on one principal surface side of the capacitor.
    Type: Application
    Filed: October 5, 2017
    Publication date: February 15, 2018
    Inventors: KOICHI KANRYO, Noriyuki Inoue, Hiromasa Saeki, Takeo Arakawa, Kazuo Hattori, Ken Ito
  • Patent number: 9865400
    Abstract: A capacitor that includes a conductive porous base material; a dielectric layer; and an electrode. The conductive porous base material, the dielectric layer, and the upper electrode are laminated together to constitute an effective part that accumulates charges in the dielectric layer when a voltage is applied between the conductive porous base material and the electrode. The conductive porous base material includes at least one groove having a width of 10 ?m or more at ½ of a depth of the at least one groove.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ken Ito, Noriyuki Inoue, Koichi Kanryo