Patents by Inventor Noriyuki Iwamori
Noriyuki Iwamori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7754580Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: GrantFiled: April 12, 2007Date of Patent: July 13, 2010Assignee: DENSO CORPORATIONInventors: Hiroaki Himi, Noriyuki Iwamori
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Publication number: 20070194413Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: ApplicationFiled: April 12, 2007Publication date: August 23, 2007Applicant: DENSO CORPORATIONInventors: Hiroaki Himi, Noriyuki Iwamori
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Patent number: 7220654Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: GrantFiled: November 20, 2003Date of Patent: May 22, 2007Assignee: Denso CorporationInventors: Hiroaki Himi, Noriyuki Iwamori
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Patent number: 6946711Abstract: In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each n+ source region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.Type: GrantFiled: June 7, 2002Date of Patent: September 20, 2005Assignee: Denso CorporationInventors: Mikimasa Suzuki, Shoji Miura, Akira Kuroyanagi, Noriyuki Iwamori, Takashi Suzuki
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Publication number: 20040108566Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: ApplicationFiled: November 20, 2003Publication date: June 10, 2004Inventors: Hiroaki Himi, Noriyuki Iwamori
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Patent number: 6676748Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: GrantFiled: November 16, 2000Date of Patent: January 13, 2004Assignee: Denso CorporationInventors: Hiroaki Himi, Noriyuki Iwamori
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Publication number: 20030218246Abstract: In a semiconductor device, a plurality of bump electrodes are formed for a source pad or a drain pad. The bump electrodes and the source or drain pad are connected with each other through wiring patterns. Thus, the following effect is produced unlike cases where one bump electrode is connected with one source pad or one drain pad through a wiring pattern: An amount of current that passes through each of the bump electrodes can be reduced, so that a breakdown of the bump electrodes is lessened.Type: ApplicationFiled: May 19, 2003Publication date: November 27, 2003Inventors: Hirofumi Abe, Hiroyuki Ban, Yoshinori Arashima, Hirokazu Itakura, Takao Kuroda, Noriyuki Iwamori, Satoshi Shiraki
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Publication number: 20030003692Abstract: In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each n+ source region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.Type: ApplicationFiled: June 7, 2002Publication date: January 2, 2003Inventors: Mikimasa Suzuki, Shoji Miura, Akira Kuroyanagi, Noriyuki Iwamori, Takashi Suzuki
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Patent number: 6337249Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.Type: GrantFiled: November 20, 2000Date of Patent: January 8, 2002Assignee: NipponDenso Co., Ltd.Inventors: Hiroyuki Yamane, Yasushi Higuchi, Mitsutaka Katada, Noriyuki Iwamori, Tsutomu Kawaguchi, Takeshi Kuzuhara
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Patent number: 6268298Abstract: In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a specific time period (equal to or longer than 15 minutes). When performing the heat treatment and when raising a temperature up to the heat treatment temperature, oxygen is supplied together with nitrogen gas (inert gas). A supply amount of oxygen is controlled to be equal to or less than 5% when raising the temperature up to the heat treatment temperature, and to be equal to or less than 2% when performing the heat treatment. After the heat treatment, the oxidation film is formed. As a result, crystal defects (OSFs) are prevented from being produced on the silicon substrate surface.Type: GrantFiled: March 9, 1999Date of Patent: July 31, 2001Assignee: Denso CorporationInventors: Atsushi Komura, Takeshi Kuzuhara, Noriyuki Iwamori, Manabu Koike, Jiro Sakata, Hirofumi Funahashi, Kenji Nakashima, Masahiko Ishii
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Patent number: 5675167Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.Type: GrantFiled: November 24, 1995Date of Patent: October 7, 1997Assignee: Nippondenso Co., Ltd.Inventors: Hiroyuki Yamane, Yasushi Higuchi, Mitsutaka Katada, Noriyuki Iwamori, Tsutomu Kawaguchi, Takeshi Kuzuhara