Patents by Inventor Noriyuki Iwamori

Noriyuki Iwamori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7754580
    Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: July 13, 2010
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Himi, Noriyuki Iwamori
  • Publication number: 20070194413
    Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.
    Type: Application
    Filed: April 12, 2007
    Publication date: August 23, 2007
    Applicant: DENSO CORPORATION
    Inventors: Hiroaki Himi, Noriyuki Iwamori
  • Patent number: 7220654
    Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: May 22, 2007
    Assignee: Denso Corporation
    Inventors: Hiroaki Himi, Noriyuki Iwamori
  • Patent number: 6946711
    Abstract: In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each n+ source region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: September 20, 2005
    Assignee: Denso Corporation
    Inventors: Mikimasa Suzuki, Shoji Miura, Akira Kuroyanagi, Noriyuki Iwamori, Takashi Suzuki
  • Publication number: 20040108566
    Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.
    Type: Application
    Filed: November 20, 2003
    Publication date: June 10, 2004
    Inventors: Hiroaki Himi, Noriyuki Iwamori
  • Patent number: 6676748
    Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: January 13, 2004
    Assignee: Denso Corporation
    Inventors: Hiroaki Himi, Noriyuki Iwamori
  • Publication number: 20030218246
    Abstract: In a semiconductor device, a plurality of bump electrodes are formed for a source pad or a drain pad. The bump electrodes and the source or drain pad are connected with each other through wiring patterns. Thus, the following effect is produced unlike cases where one bump electrode is connected with one source pad or one drain pad through a wiring pattern: An amount of current that passes through each of the bump electrodes can be reduced, so that a breakdown of the bump electrodes is lessened.
    Type: Application
    Filed: May 19, 2003
    Publication date: November 27, 2003
    Inventors: Hirofumi Abe, Hiroyuki Ban, Yoshinori Arashima, Hirokazu Itakura, Takao Kuroda, Noriyuki Iwamori, Satoshi Shiraki
  • Publication number: 20030003692
    Abstract: In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each n+ source region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.
    Type: Application
    Filed: June 7, 2002
    Publication date: January 2, 2003
    Inventors: Mikimasa Suzuki, Shoji Miura, Akira Kuroyanagi, Noriyuki Iwamori, Takashi Suzuki
  • Patent number: 6337249
    Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: January 8, 2002
    Assignee: NipponDenso Co., Ltd.
    Inventors: Hiroyuki Yamane, Yasushi Higuchi, Mitsutaka Katada, Noriyuki Iwamori, Tsutomu Kawaguchi, Takeshi Kuzuhara
  • Patent number: 6268298
    Abstract: In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a specific time period (equal to or longer than 15 minutes). When performing the heat treatment and when raising a temperature up to the heat treatment temperature, oxygen is supplied together with nitrogen gas (inert gas). A supply amount of oxygen is controlled to be equal to or less than 5% when raising the temperature up to the heat treatment temperature, and to be equal to or less than 2% when performing the heat treatment. After the heat treatment, the oxidation film is formed. As a result, crystal defects (OSFs) are prevented from being produced on the silicon substrate surface.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: July 31, 2001
    Assignee: Denso Corporation
    Inventors: Atsushi Komura, Takeshi Kuzuhara, Noriyuki Iwamori, Manabu Koike, Jiro Sakata, Hirofumi Funahashi, Kenji Nakashima, Masahiko Ishii
  • Patent number: 5675167
    Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.
    Type: Grant
    Filed: November 24, 1995
    Date of Patent: October 7, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hiroyuki Yamane, Yasushi Higuchi, Mitsutaka Katada, Noriyuki Iwamori, Tsutomu Kawaguchi, Takeshi Kuzuhara