Patents by Inventor Noriyuki Kajihara

Noriyuki Kajihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070132702
    Abstract: A display driving integrated circuit includes: a tone display reference voltage generating circuit for generating 64 tone display reference voltages by resistive division on the basis of a predetermined reference voltage; D/A conversion circuits each for performing an analog conversion with respect to display data on the basis of the 64 tone display reference voltages; and 64 reference voltage wires provided in parallel, via which the 64 tone display reference voltages are supplied to the D/A conversion circuits, respectively. The 64 reference voltage wires are provided so that a potential difference corresponds to two tones or more between adjacent two reference voltage wires.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 14, 2007
    Inventors: Noriyuki Kajihara, Hiroaki Fujino, Tomoaki Nakao, Yukihisa Orisaka, Eisaku Miyazaki, Michihiro Nakahara, Yasuhiro Nishida, Masahiko Monomohshi
  • Patent number: 6963325
    Abstract: In a display driving apparatus of the present invention and a liquid display apparatus using the same, a DC current is supplied to a reference voltage generating circuit from both ends of a resistance of the resistance divided circuit, via a bypass circuit, which is a bypass other than a route from a power source. This arrangement allows the reference voltage generating circuit itself to compensate current supply ability of a reference voltage supplied from the power source, even if an output circuit is omitted from the arrangement, thereby preventing a waveform of a gradation display voltage from having non-sharp rising and falling edges, or preventing variation in voltage due to charging and discharging of a pixel capacitor. This ensures an accurate gradation display voltage.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: November 8, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Yano, Noriyuki Kajihara, Yukihisa Orisaka
  • Patent number: 6762737
    Abstract: A source driver 92 of the present invention has a reference voltage generator 38 for generating tone display voltages, and a DA converter 36 for selecting and outputting a tone display voltage to a liquid crystal panel. In the source driver 92, a buffer circuit section 41 is provided between the reference voltage generator 38 and the DA converter 36. The buffer circuit section 41 includes a buffer, and analog switch circuits which switch modes of connection between the reference voltage generator 38, the buffer, and the DA converter 36, so as to select whether to output the tone display voltage to the DA converter 36 via the buffer or without utilizing the buffer. Operations of the analog switch circuits are controlled by the analog switch circuit section 40.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: July 13, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noriyuki Kajihara, Toshio Watanabe, Masafumi Katsutani
  • Patent number: 6677923
    Abstract: The present invention includes: standard voltage producing means for producing 2n tone display voltages from incoming first reference voltages in accordance with n-bit display data; and selecting means for selecting a voltage from the 2n tone display voltages in accordance with incoming display data, for transmission to a liquid crystal panel through a plurality of output terminals with no further processing, wherein the standard voltage producing means includes: generation means for generating a second reference voltage from adjacent two of the first reference voltages arranged in ascending or descending order, the second reference voltage having an intermediate level between those of the adjacent first reference voltages; buffer means for impedance-converting the second reference voltage for output; and voltage dividing means for producing a voltage having an intermediate level between those of the adjacent first reference voltages and of adjacent ones of the first and second reference voltages by vol
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 13, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noriyuki Kajihara, Yoshinori Ogawa
  • Publication number: 20030052851
    Abstract: In a display driving apparatus of the present invention and a liquid display apparatus using the same, a DC current is supplied to a reference voltage generating circuit from both ends of a resistance of the resistance divided circuit, via a bypass circuit, which is a bypass other than a route from a power source. This arrangement allows the reference voltage generating circuit itself to compensate current supply ability of a reference voltage supplied from the power source, even if an output circuit is omitted from the arrangement, thereby preventing a waveform of a gradation display voltage from having non-sharp rising and falling edges, or preventing variation in voltage due to charging and discharging of a pixel capacitor. This ensures an accurate gradation display voltage.
    Type: Application
    Filed: June 24, 2002
    Publication date: March 20, 2003
    Inventors: Takeshi Yano, Noriyuki Kajihara, Yukihisa Orisaka
  • Publication number: 20020050970
    Abstract: A source driver 92 of the present invention has a reference voltage generator 38 for generating tone display voltages, and a DA converter 36 for selecting and outputting a tone display voltage to a liquid crystal panel. In the source driver 92, a buffer circuit section 41 is provided between the reference voltage generator 38 and the DA converter 36. The buffer circuit section 41 includes a buffer, and analog switch circuits which switch modes of connection between the reference voltage generator 38, the buffer, and the DA converter 36, so as to select whether to output the tone display voltage to the DA converter 36 via the buffer or without utilizing the buffer. Operations of the analog switch circuits are controlled by the analog switch circuit section 40.
    Type: Application
    Filed: October 12, 2001
    Publication date: May 2, 2002
    Inventors: Noriyuki Kajihara, Toshio Watanabe, Masafumi Katsutani
  • Publication number: 20020036609
    Abstract: The present invention includes:
    Type: Application
    Filed: September 28, 2001
    Publication date: March 28, 2002
    Inventors: Noriyuki Kajihara, Yoshinori Ogawa
  • Patent number: 6297596
    Abstract: A power supply circuit includes a reference voltage generation circuit to generate reference voltages, an operational amplifier to receive a first reference voltage and an intermediate voltage, an operational amplifier to receive a second reference voltage and the intermediate voltage, an output buffer which includes a pair of transistors controlled to turn on/off according to outputs of the two operational amplifiers and generates the intermediate voltage, and a through current prevention circuit to prevent a through current supplied to the pair of transistors in the output buffer. The through current prevention circuit operates to turn off one of the pair of transistors when the other turns on. Thus, the through current in the pair of transistors can be prevented.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: October 2, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Noriyuki Kajihara
  • Patent number: 5798741
    Abstract: A liquid crystal panel is driven with small number of kinds of voltage. First and second common voltages V0, V4 are generated symmetrically above and under the central common voltage V2 in the common voltage source. First and second segment voltages V1, V3 are generated symmetrically above and under the central common voltage V2 in the segment voltage source. Adjustment of contrast may be facilitated by adjusting common voltages and segment voltages independently or each other. Power may be realized by equalizing the segment voltages and the central common voltage when there is no display.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 25, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Noriyuki Kajihara