Abstract: A fabricating apparatus (2) of an sic epitaxial wafer disclosed herein includes: a growth furnace (100A); a gas mixing preliminary chamber (107) disposed outside the growth furnace and configured to mix carrier gas and/or material gas and to regulate a pressure thereof; a wafer boat (210) configured so that a plurality of SiC wafer pairs (200WP), in which two substrates each having an SiC single crystal in contact with each other in a back-to-back manner, are disposed at equal intervals with a gap therebetween; and a heating unit (101) configured to heat the wafer boat disposed in the growth furnace to an epitaxial growth temperature. The carrier gas and/or the material gas are introduced into the growth furnace after preliminarily being mixed and pressure-regulated in the gas mixing preliminary chamber (107) to grow an SiC layer on a surface of each of the plurality of SiC wafer pairs.

Abstract: A semiconductor substrate (1) disclosed herein includes: an SiC single crystal substrate (10SB); a graphene layer (11GR) disposed on an Si plane of the SiC single crystal substrate (10SB); an SiC epitaxial growth layer (12RE) disposed above the SiC single crystal substrate (10SB) via the graphene layer (11GR); and a polycrystalline Si layer (15PS) disposed on an Si plane of the SiC epitaxial growth layer (12RE). The semiconductor substrate may include a graphite substrate or an silicon substrate disposed on a polycrystalline Si layer (15PS). The semiconductor substrate may further include an SiC polycrystalline growth layer (18PC) disposed on a C plane of the SiC epitaxial growth layer (12RE). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.

Abstract: A semiconductor substrate (1) according to an embodiment includes: a hexagonal SiC single crystal layer (13I); an SiC epitaxial growth layer (12E) disposed on an Si plane of an SiC single crystal layer (13I); and an SiC polycrystalline growth layer (18PC) disposed on a C plane opposite to the Si plane of the SiC single crystal layer (13I). The SiC single crystal layer (13I) includes a single crystal SiC thin layer (10HE) obtained by weakening the hydrogen ion implantation layer (10HI), and a phosphorus ion implantation layer (10PI). The phosphorus ion implantation layer (10PI) is disposed between the single crystal SiC thin layer (10HE) and the SiC polycrystalline growth layer (18PC). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.

Abstract: A semiconductor substrate (1) includes: an SiC single crystal substrate (10SB), a first graphene layer (11GR1) disposed on an Si plane of the SiC single crystal substrate 10SB; an SiC epitaxial growth layer (12RE) formed above the SiC single crystal substrate via the first graphene layer; and a second graphene layer (11GR2) disposed on an Si plane of the SiC epitaxial growth layer. There is also included an SiC polycrystalline substrate (16P) provisionally bonded onto the SiC epitaxial growth layer via the second graphene layer. The SiC single crystal substrate is able to be reused by being separated from the SiC epitaxial growth layer. This semiconductor substrate further includes an SiC polycrystalline growth layer (18PC) CVD grown on the C plane of the SiC epitaxial growth layer; and the SiC epitaxial growth layer is transferred to the SiC polycrystalline growth layer.

Abstract: Systems and methods for growth of silicon carbide over a layer comprising graphene and/or hexagonal boron nitride, and related articles, are generally described. In some embodiments, a SiC film is fabricated over a layer comprising graphene and/or hexagonal boron nitride, which in turn is disposed over a substrate. The layer and/or the substrate may be lattice-matched with the SiC film to reduce defect density in the SiC film. The fabricated SiC film may then be removed from the substrate via, for example, a stressor attached to the SiC film. In certain cases, the layer serves as a reusable platform for growing SiC films and also serves a release layer that allows fast, precise, and repeatable release at the layer surface.

Abstract: A nonvolatile memory device improves the accuracy of screening testing while applying a voltage at or lower than the limit of the withstand voltage of an element for high voltage in the screening testing. The nonvolatile memory device includes a high voltage production circuit that produces a high voltage, a high voltage waveform conversion circuit to which the high voltage is input and which converts the voltage waveform, and a memory cell section provided with memory cells in which data rewriting is performed as a result of applying the converted high voltage. The high voltage waveform conversion circuit includes a test signal input section TEST and applies the high voltage input from the high voltage production circuit to the memory cell section without converting the voltage waveform when a test signal is input to the test signal input section.

Abstract: A nonvolatile memory device improves the accuracy of screening testing while applying a voltage at or lower than the limit of the withstand voltage of an element for high voltage in the screening testing. The nonvolatile memory device includes a high voltage production circuit that produces a high voltage, a high voltage waveform conversion circuit to which the high voltage is input and which converts the voltage waveform, and a memory cell section provided with memory cells in which data rewriting is performed as a result of applying the converted high voltage. The high voltage waveform conversion circuit includes a test signal input section TEST and applies the high voltage input from the high voltage production circuit to the memory cell section without converting the voltage waveform when a test signal is input to the test signal input section.