Abstract: A timing edge forming circuit includes a pattern generator for generating address data, a rate signal and pattern data, a first logic delay circuit for generating first delay time data by the address data wherein the first delay time data includes a first multiple delay time which is an integer multiple of one cycle of the clock signal and a first fractional delay time which is smaller than one cycle of the clock signal, and for sending an enable signal in synchronism with the clock signal which is delayed by the first multiple delay time and the first fractional delay time, a logic delay control circuit for adding the first fractional delay time to skew data to form second delay time data, a second logic delay circuit for providing a second multiple delay time in the second delay time data which is an integer multiple of one cycle of the clock signal to the enable signal, and for producing a second fractional delay time which is smaller than one cycle of the clock signal, a variable delay circuits for provid

Abstract: Pattern data comprising N=8 words, where one word comprises m=3 bits, delivered in parallel from a pattern memory 2 is input to a parallel/serial conversion circuit 3. The circuit 3 can be switched between a serial output mode (MC="0") in which data for one word per pin is serially delivered every test cycle and a parallel-serial output mode in which parallel data for n-2 words per pin (m.times.n bits) are serially delivered every test cycle in response to a mode control signal MC.

Abstract: A timing generating circuit formed as an LSI of CMOS.FETs is provided which enables correction of the variations of delay amount caused by the heat generated in the CMOS.FETs due to the propagation of pulses through the CMOS.FETs. A sub delay element 22 is connected in series to a main delay element 21 in which a timing is set and placed in the vicinity of the element 21. Both delay elements are connected in the same cell structure and arrangement. The sum of initial values of the delay amounts of respective delay elements is made to be a constant value. An input pulse to the main delay element is also supplied to a reference signal generator part 27 which outputs a reference signal using a reference clock after the lapse of the constant value from the time the input pulse is inputted. A time difference between this reference signal and the output from the sub delay element 22 is detected by a time difference detection part 29.

Abstract: A temperature compensation circuit which includes a signal detecting circuit provided on a signal supply path which outputs logic signals to a target circuit. Also included are switch elements which turn current on/off to heater elements each time the signal detecting circuit detects that the logic signals are being applied to the target circuit. The power source of the invention therefore only needs to endure the same amount of current applied to the target circuit which leads to a reduction in power consumption.

Abstract: A timing generator for generating delay timing signals which have delay time up to n-times of a reference clock period is capable of considerably reducing the hardware size. The timing generator is used in a semiconductor testing apparatus. The timing generator can contribute to reduce the total size and cost of the semiconductor testing apparatus. The timing generator includes a counter for counting the reference clock, an adder for adding the output of the counter to delay data, a series of registers for storing the output of the adder and shifting the output of the adder in synchronism with a delay trigger signal, a series of exclusive OR gates for comparing each output of the registers with the output of the counter and generating coincidence signals when the output from the register and the counter coincide with each other, and an OR gate for receiving the outputs of the exclusive OR gates and generating a signal which is combined of the outputs from the exclusive OR gates.

Abstract: A seat belt winding device for motor vehicles of the type for winding up two seat belts upon a single winding device shaft one over the other including a shaft for winding the two seat belts upon, means for causing the shaft to rotate in the windup direction when the two seat belts are extended and a pressure board resiliently engaging with the outside surface of the seat belts wound on the shaft whereby a pressure is always applied to the two seat belts when they are extended.