Patents by Inventor Noriyuki Soejima

Noriyuki Soejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5945691
    Abstract: In order to inhibit destruction during a turn-off state, a cathode electrode (6) is not connected to the overall major surface of a semiconductor substrate (10), but selectively connected to a region which is substantially opposed to an anode electrode (5). When a forward voltage is applied, therefore, an electric field which is generated in the semiconductor substrate (10) is distributed substantially only in a region immediately under a P-type diffusion layer (2), to hardly spread into a peripheral region positioned outside the region. Consequently, carriers which are injected from the P-type diffusion layer (2) and an N.sup.+ layer (4) into an N.sup.- layer (1) hardly spread to the peripheral region, but are stored substantially only in the region immediately under the P-type diffusion layer (2). Thus, concentration of a reverse current is relieved during a turn-off state in a peripheral edge portion of the P-type diffusion layer (2).
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: August 31, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshifumi Tomomatsu, Mitsuyoshi Takeda, Noriyuki Soejima
  • Patent number: 5811873
    Abstract: A diode has a semiconductor layer which has a predetermined impurity concentration, and in which the rate of extension of a depletion layer during a reverse recovery operation gradually decreases so as to decrease the rate of change in reverse recovery current. In addition, the number of excess carriers accumulated in the semiconductor layer during a forward operation is decreased so as to decrease reverse recovery charge. The diode generates less surge voltage and loss and can comply with operating conditions of various forward current densities, and various reverse voltages.
    Type: Grant
    Filed: November 24, 1995
    Date of Patent: September 22, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Noriyuki Soejima
  • Patent number: 5717244
    Abstract: An N.sup.- layer (11) of a low impurity concentration is formed on an upper major surface of an N.sup.+ layer (13) of a high impurity concentration in a diode (10). A P layer (12) is further formed on its upper major surface. The N.sup.- layer (11) is in a multilayer structure of first to third regions (11a to 11c) having carrier lifetimes .tau..sub.1, .tau..sub.2 and .tau..sub.3 respectively. These lifetimes are in relation .tau..sub.2 <.tau..sub.1 <.tau..sub.3. Due to the large lifetime .tau..sub.3 of the third region (11c), soft recovery can be implemented. The fact that the lifetime .tau..sub.3 of the third region (11c) is large serves as a factor reducing a forward voltage V.sub.f. It is possible to attain soft recovery without increasing the forward voltage V.sub.F by properly designing these lifetimes and thicknesses.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: February 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Noriyuki Soejima