Patents by Inventor Noriyuki Sugihara
Noriyuki Sugihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7696744Abstract: A screw-less latching system for securing load boards comprises a frame and a backer plate. The frame includes a loading site for a device under test. The loading site includes a first tee clamp disposed along a first longitudinal axis and a second tee clamp disposed along a second longitudinal axis of the loading site. The loading site further includes a first spring plunger disposed along a first lateral axis of the loading site. The backer plate is configured to attach the device under test. The backer plate includes two lock tabs coupling with the first and second tee clamps. The backer plate further includes a first recess coupling with the first spring plunger.Type: GrantFiled: November 29, 2007Date of Patent: April 13, 2010Assignee: Verigy(Singapore) Pte. Ltd.Inventors: Todd James Sholl, Noriyuki Sugihara, Sanjeev Grover, Stephen Bellato, Benson Morris
-
Publication number: 20090141463Abstract: A screw-less latching system for securing load boards comprises a frame and a backer plate. The frame includes a loading site for a device under test. The loading site includes a first tee clamp disposed along a first longitudinal axis and a second tee clamp disposed along a second longitudinal axis of the loading site. The loading site further includes a first spring plunger disposed along a first lateral axis of the loading site. The backer plate is configured to attach the device under test. The backer plate includes two lock tabs coupling with the first and second tee clamps. The backer plate further includes a first recess coupling with the first spring plunger.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Inventors: Todd James Sholl, Noriyuki Sugihara, Sanjeev Grover, Stephen Bellato, Benson Morris
-
Patent number: 7281181Abstract: In one embodiment, an automated circuit test system is calibrated by electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, and then executing an AC timing calibration procedure to determine a timing delay for each of a first set of relationships. A second calibration unit is then electrically coupled between the plurality of drivers and comparators, and an AC timing calibration procedure is executed to determine a timing delay for each of a second set of relationships. The first and second calibration units comprise fixed wiring paths that respectively couple pairs of the drivers and comparators in accord with the first and second sets of relationships. A set of equations is solved based on the timing delays and driver/comparator relationships to determine relative timing errors introduced by signal paths of the test system including the drivers and comparators.Type: GrantFiled: June 27, 2005Date of Patent: October 9, 2007Assignee: Verigy (Singapore) Pte. Ltd.Inventor: Noriyuki Sugihara
-
Publication number: 20070089858Abstract: A waterblock and accompanying cooling tube for carrying away heat generated by electrical or electronic components mounted on a circuit board or other substrate are disclosed. The cooling tube is attached to the waterblock by means of an adhesive or other suitable material, and is not positioned in a groove machined into the surface of the waterblock as has been done in past. The unique design of the waterblock and cooling tube eliminates the need to machine expensive grooves in the waterblock, thereby reducing manufacturing costs.Type: ApplicationFiled: October 25, 2005Publication date: April 26, 2007Inventors: John Andberg, Noriyuki Sugihara
-
Publication number: 20070022347Abstract: In one embodiment, an automated circuit test system is calibrated by electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, and then executing an AC timing calibration procedure to determine a timing delay for each of a first set of relationships. A second calibration unit is then electrically coupled between the plurality of drivers and comparators, and an AC timing calibration procedure is executed to determine a timing delay for each of a second set of relationships. The first and second calibration units comprise fixed wiring paths that respectively couple pairs of the drivers and comparators in accord with the first and second sets of relationships. A set of equations is solved based on the timing delays and driver/comparator relationships to determine relative timing errors introduced by signal paths of the test system including the drivers and comparators.Type: ApplicationFiled: June 27, 2005Publication date: January 25, 2007Inventor: Noriyuki Sugihara
-
Patent number: 7147499Abstract: In one embodiment, a mating circuit assembly is coupled and decoupled to a system by 1) mechanically and electrically coupling at least a first interposer, mounted on at least one of first and second substrates, to the mating circuit assembly. The mechanical and electrical coupling is accomplished using at least first and second spring mechanisms, with the first and second spring mechanisms being mounted between the connector housing and respective ones of the first and second substrates. At least one of the first and second substrates transmits signals between the first interposer and the system. The first interposer is electrically and mechanically decoupled from the mating circuit assembly by creating a vacuum between the connector housing and at least one of the first and second substrates. Other embodiments are also disclosed.Type: GrantFiled: October 19, 2005Date of Patent: December 12, 2006Assignee: Verigy IPcoInventors: Romi Mayder, John W. Andberg, Don Chiu, Noriyuki Sugihara
-
Patent number: 6570397Abstract: Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time.Type: GrantFiled: August 7, 2001Date of Patent: May 27, 2003Assignee: Agilent Technologies, Inc.Inventors: Romi Mayder, Noriyuki Sugihara, Andrew Tse, Randy L. Bailey
-
Publication number: 20030030453Abstract: Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time.Type: ApplicationFiled: August 7, 2001Publication date: February 13, 2003Inventors: Romi Mayder, Noriyuki Sugihara, Andrew Tse, Randy L. Bailey
-
Patent number: 6270145Abstract: In order to prevent the entrance of water or other liquids into the inside of a canvas top, to prevent the occurrence of wrinkles and a positional shift at the time of assembling the canvas top, to prevent wind noise generated at the time of vehicle running, and to increase the work efficiency for assembling the canvas top, a flap 11 provided with a hook 10 is attached to the rear end portion (a canvas 6a of a depending portion 6 of a top deck 7) of a canvas covering an open portion 3 of an automobile, and the rear end portion 6a of the canvas is attached to a vehicle body in a state in which the hook 10 is engaged with an engagement portion (an engagement groove 17 in a garnish 15) provided on the vehicle body side.Type: GrantFiled: July 13, 1999Date of Patent: August 7, 2001Assignee: Suzuki Motor CorporationInventors: Mitsuhiro Kamo, Noriyuki Sugihara
-
Patent number: 6176040Abstract: An automotive door stopper device has a decreased vertical dimension to facilitate the arrangement of the device within a door opening of a vehicle body, and prevents the entrance of foreign matter and the accumulation of dirt and dust in the device. The automotive door stopper device includes a lever having a base end portion rotatably attached to a side of a door, an engagement pin fixed to the vehicle body for guiding the lever, and a braking mechanism for restraining movement of the lever. A planar surface of the lever faces the vertical direction. A case is provided which houses the braking mechanism and covers a portion of the lever. The case is secured to the vehicle body by the engagement pin. The automotive door stopper device allows the door to be stopped in an intermediate position between the open and closed positions.Type: GrantFiled: March 18, 1999Date of Patent: January 23, 2001Assignee: Suzuki Motor CorporationInventor: Noriyuki Sugihara
-
Patent number: 4409543Abstract: An apparatus is disclosed for determining the impedance and dissipation factor of a capacitive and/or inductive device and to reduce measurement error by digital calculation and manipulation. A synchronous rectifying means, a phase shifter and a detecting means are employed to detect the in-phase and orthogonal components of the current through a device and to compare it to a reference voltage impressed across the device. An arithmetical calculation using the values of these components determines the impedance and the dissipation factor of the device.Type: GrantFiled: March 5, 1981Date of Patent: October 11, 1983Assignee: Hewlett-Packard CompanyInventor: Noriyuki Sugihara
-
Patent number: 4306297Abstract: An apparatus is disclosed for determining the vector voltage ratio of two a.c. input signals. A synchronous rectifying circuit, a phase shifter and a voltmeter are employed to detect the in-phase and orthogonal components of the input signals relative to a reference signal. A calculation section determines the vector voltage ratio from the values of these components.Type: GrantFiled: January 25, 1980Date of Patent: December 15, 1981Assignee: Hewlett-Packard CompanyInventors: Noriyuki Sugihara, Takashi Yoshida