Abstract: A data transferring system in which detecting a route from an upper position to a lower position on a tree structure is realized by hardware of communication devices and processes for detecting the above are simplified is disclosed. A root complex broadcasts a search message to a lower node on a tree structure. When a port of the node confirms and receives the search message, the port adds its own information, specifically, the device number of the port, to the data payload part of the search message and sends the search message including the information to a node (end point) located at the lowest position on the tree structure. When the end point receives the search message, the end point sends a reply message to the root complex. The device numbers of the ports where the search message passes through are attached to the reply message.

Abstract: A communication apparatus is disclosed that includes a transmission circuit configured to transmit transmission data to a communication counterpart; a reception circuit configured to receive reception data from the communication counterpart; a storage device configured as at least two buffers including a transmission buffer that stores the transmission data and a reception buffer that stores the reception data; and an address mapping unit configured to perform address mapping of the buffers including the transmission buffer and the reception buffer on the storage device, and adjust the storage capacity of the transmission buffer and the storage capacity of the reception buffer.

Abstract: A data transferring system based on the PCI Express standard in which power saving is realized is disclosed. In the data transferring system, a data transferring device transfers image data based on the PCI Express standard by synchronizing with a line synchronizing signal LSYNC. At this time, the data transferring device causes a period between packets (image data) to be transferred in one line cycle of the line synchronizing signal LSYNC to be shorter than a transition period “t1” which is required to transit from a link state L0 to a link state L0s and from the link state L0s to the link state L0. With this, the number of the transition periods “t1” is reduced and the period of the link state L0s is made long.

Abstract: A subband processing apparatus useful for wavelet conversion and compression-decompression operation includes a plurality of memories and a plurality of analytic filter banks. The plurality of memories store an input signal in a way such that the input signal is divided into a plurality of regional signals to correspond to the plurality of memories. The plurality of analytic filter banks analyzes in parallel the regional signals. Each analytic filter bank is configured to be in a one-to-one relationship with one of the plurality of memories. In this apparatus, each of the plurality of memories stores a corresponding regional signal other signal copied from the leading and trailing portions of other stored regional signals. Reverse processing is provided to synthesize a signal from a plurality of analyzed subband signals.

Abstract: A data transfer system using a high-speed serial interface system that forms a tree structure in which point-to-point communication channels are established for data sending and data receiving independently is provided. The data transfer system includes plural end points each having plural upper ports each of which is connected to a switch of an upper side, wherein each end point includes a port selecting part for selecting a port to be used according to an operation mode of the data transfer system so as to dynamically change the tree structure.

Abstract: A subband processing apparatus useful for wavelet conversion and compression-decompression operations includes a plurality of memories and a plurality of analytic filter banks. The plurality of memories store an input signal in a way such that the input signal is divided into a plurality of regional signals to correspond to the plurality of memories. The plurality of analytic filter banks analyzes in parallel the regional signals. Each analytic filter bank is configured to be in a one-to-one relationship with one of the plurality of memories. In this apparatus, each of the plurality of memories stores a corresponding regional signal and at least one other signal copied from the leading and trailing portions of other stored regional signals. Reverse processing is provided to synthesize a signal from a plurality of analyzed subband signals.

Abstract: An image forming system comprising a serial communication control part, an image input part, an image output part, an image processing part, a storage part, a printer controller, and a high-speed serial bus. The high-speed serial bus mutually couples the serial communication control part and at least one of the image input part, the image output part, the image processing part, the storage part and the printer controller.

Abstract: An imaging system that implements a PCI Express high-speed serial interface system is disclosed in which a plurality of point-to-point simplex communication channels are established to realize a data communication network having a tree structure. The imaging system includes a PCI Express high-speed serial interface, and plural independent image processing units as end point devices of the tree structure that are connected by the PCI Express high-speed serial interface.

Abstract: A subband processing apparatus useful for wavelet conversion and compression-decompression operations includes a plurality of memories and a plurality of analytic filter banks. The plurality of memories store an input signal in a way such that the input signal is divided into a plurality of regional signals to correspond to the plurality of memories. The plurality of analytic filter banks analyzes in parallel the regional signals. Each analytic filter bank is configured to be in a one-to-one relationship with one of the plurality of memories. In this apparatus, each of the plurality of memories stores a corresponding regional signal and at least one other signal copied from the leading and trailing portions of other stored regional signals. Reverse processing is provided to synthesize a signal from a plurality of analyzed subband signals.

Abstract: A photoelectric transfer device includes at least one photoelectric transfer cell having the following elements: A photoelectric transfer element generates a photoelectric current based on a quantity of incident light. An amplifier element includes first FET and functions as a source follower in which a source voltage of the first FET is varied so as to follow up a gate voltage thereof. A read unit outputs, as an output signal, the source voltage of the source follower. The photoelectric transfer element is connected to a gate and source of the amplifier element so that a voltage between the gate and source of the amplifier element is applied across the photoelectric transfer element.

Abstract: A method for manufacturing a C-MOS thin film transistor device has the steps of implanting the n-type impurity only in the upper layer portion of the source-drain section of the n-channel transistor by controlling implantation energy of the n-type impurity; implanting the p-type impurity in the source-drain section and the gate electrode of the p-channel transistor, and the source-drain section and the gate electrode of the n-channel transistor by controlling implantation energy of the p-type impurity; and activating the implanted n-type and p-type impurities in the source-drain section of the n-channel transistor, and activating the implanted p-type impurity in the source-drain section and the gate electrode of the p-channel transistor and gate electrode of the n-channel transistor. The n-type and the p-type may be respectively changed to the p-type and the n-type in the above construction.

Abstract: A shift register circuit comprises a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, where a first one of the first clocked gate inverters is adapted to receive an input pulse signal, an output line connected to an output of each of the inverters for outputting an output pulse signal, and a second clocked gate inverter connected to the output of each of the inverters for outputting an output pulse signal. The first clocked gate inverters operate responsive to a first clock signal, and the second clocked gate inverters operate responsive to a second clock signal which is different from the first clock signal.