Abstract: A clock generator for supplying one or more clock signals to integrated circuits within a processor-based system is disclosed. The clock generator includes one or more PLLs and one or more configuration registers. The clock is supplied power from two different voltage sources, such that, during a standby mode of the system, the configuration registers continue to be powered with the lower of the two voltages while the PLLs are turned off. Upon returning from the standby mode, the clock generator is reinitialized according to a user-defined configuration, since the configuration registers retain data throughout standby mode. Alternatively, the clock generator may be reinitialized to a default state following standby mode, for backwards compatibility with prior art clock generators.