Abstract: A semiconductor fabrication facility (fab) configuration module is defined to virtually model physical systems and attributes of a fab. A data acquisition module is defined to interface with the physical systems of the fab and gather operational data from the physical systems. A visualizer module is defined to collect and aggregate the operational data gathered from the physical systems. The visualizer module is further defined to process the operational data into a format suitable for visual rendering. The processed operational data is displayed within a visual context of the fab in a graphical user interface controlled by the visualizer module. An analyzer module is defined to analyze data collected by the visualizer module and to resolve queries regarding fab performance. An optimizer module is defined to control systems within the fab in response to data collected by the visualizer module, data generated by the analyzer module, or a combination thereof.

Abstract: A semiconductor fabrication facility (fab) configuration module is defined to virtually model physical systems and attributes of a fab. A data acquisition module is defined to interface with the physical systems of the fab and gather operational data from the physical systems. A visualizer module is defined to collect and aggregate the operational data gathered from the physical systems. The visualizer module is further defined to process the operational data into a format suitable for visual rendering. The processed operational data is displayed within a visual context of the fab in a graphical user interface controlled by the visualizer module. An analyzer module is defined to analyze data collected by the visualizer module and to resolve queries regarding fab performance. An optimizer module is defined to control systems within the fab in response to data collected by the visualizer module, data generated by the analyzer module, or a combination thereof.

Abstract: The present invention comprises a distal rest pad for supporting a portion of a wafer seated on an end effector. In one embodiment, the rest pad includes a bottom support pad and an edge stop. Each element is mounted separately to the distal end of a support plate. The bottom support pad includes an inclined surface that transitions to a substantially horizontal surface at its distal end. The edge stop has a substantially vertical wafer contact surface that the peripheral edge of a wafer eventually contacts as the wafer is urged towards the distal rest pad. In another embodiment, the bottom support pad comprises an inclined surface. In yet another embodiment, the distal rest pad comprises a single structure. This distal rest pad includes a backstop portion and a bottom support separated by a particle collection groove. The bottom support may include an inclined lead-in surface that transitions into a flat contact surface or only comprise an inclined lead-in surface.

Abstract: Methods and apparatuses for forming an oxide film. The method includes depositing an oxide film on a substrate using a process gas mixture that comprises a silicon source gas, an oxygen gas, and a hydrogen gas, and a process temperature between 800° C. and 1300° C. During the deposition of the oxide film, the process gas mixture comprises less than 6% oxygen, silicon gas, and predominantly hydrogen.

Abstract: Methods and apparatuses for forming an oxide film. The method includes depositing an oxide film on a substrate using a process gas mixture that comprises a silicon source gas, an oxygen gas, and a hydrogen gas, and a process temperature between 800° C. and 1300° C. During the deposition of the oxide film, the process gas mixture comprises less than 6% oxygen, silicon gas, and predominantly hydrogen.

Abstract: According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. A silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.

Abstract: A method comprising introducing a crystalline film with silicon germanium over the surface of a semiconductor substrate, and introducing a junction region by an implant of a dopant into the crystalline film. An apparatus comprising a semiconductor substrate having an active region and comprising a crystalline film comprising germanium in the active region, a gate electrode overlying the crystalline layer, and junction regions formed in the substrate adjacent opposite sides of the gate electrode.

Abstract: According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. A silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.

Abstract: A semiconductor substrate processing chamber provides a bi-directional process gas flow for deposition or etching processes. The bi-directional gas flow provides uniformity of deposition layer thickness or uniformity of etching without the need to rotate the substrate. Junctions are provided at opposite ends of a processing chamber. Inlet and outlet ports are provided on each junction. Inlet and outlet ports on opposite junctions cooperate to provide a gas flow in a first direction for half of the process cycle, and in a second direction for the other half of the process cycle.

Abstract: According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. A silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.

Abstract: A method for determining a wafer characteristic, such as the surface quality of a film formed on the wafer, using a film thickness monitor is described. In one embodiment, the method comprises the following steps. A measured spectrum for a processed wafer is generated. A set of parameters is chosen and then used to generate a calculated spectrum. The measured spectrum is compared to the calculated spectrum to determine if the two spectra match. If the two spectra do not match or the degree of nonconformity between the two spectra is greater than an acceptable error value, then there is probably a defect with the processed wafer. For example, the film formed on the wafer may have a nonuniform or hazy surface quality.

Abstract: According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. A silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.

Abstract: The present invention is a single wafer reactor having a vented lower liner for heating exhaust gas. The apparatus of the present invention includes a reaction chamber. A wafer support member which divides the chamber into an upper and lower portion is positioned within the chamber. A gas outlet for exhausting gas from the chamber has a vent to exhaust gas from the lower portion of the chamber and an exhaust passage opening to exhaust gas from the upper portion of the chamber. Heated inert purge gas is fed from the lower chamber portion through the vent at a rate so as to prevent the deposition gas from condensing in the exhaust passage.

Abstract: An improved delineation pattern for epitaxial depositions is created by forming a mask on a single-crystal silicon substrate which leaves an area (10) of the substrate exposed, doping the area with a dopant to create a doped region defined by a periphery, anisotropically, vertically etching the doped region to create a delineation pattern corresponding to the periphery, and then forming an epitaxial layer over the substrate and doped region. The periphery of the delineation pattern has a squared-off delineation step including a first step wall generally perpendicular to the surface of the substrate and a second step wall generally parallel to the surface of the substrate. The squared-off delineation step helps prevent wash-out of the delineation pattern as one or more epitaxial layers are deposited on the substrate.

Abstract: The present invention is a single wafer reactor having a vented lower liner for heating exhaust gas. The apparatus of the present invention includes a reaction chamber. A wafer support member which divides the chamber into an upper and lower portion is positioned within the chamber. A gas outlet for exhausting gas from the chamber has a vent to exhaust gas from the lower portion of the chamber and an exhaust passage opening to exhaust gas from the upper portion of the chamber. Heated inert purge gas is fed from the lower chamber portion through the vent at a rate so as to prevent the deposition gas from condensing in the exhaust passage.

Abstract: A process and apparatus is disclosed for providing access to the interior of a vacuum deposition chamber in a vacuum deposition apparatus without exposing residues, such as chlorosilane residues, within the chamber to moisture and/or oxygen-containing gases. The process comprises first placing over the upper surface of the vacuum deposition apparatus an enclosure which has a bottom opening large enough to completely cover the top opening to the chamber, and which is capable of being filled with one or more non-reactive gases. One or more non-reactive gases are then flowed into the enclosure to purge moisture and/or oxygen-containing gases from the enclosure. After the enclosure has been mounted on the apparatus and purged by the flow of non-reactive gases therein, the vacuum deposition chamber may be opened, while continuing the flow of non-reactive gases into the enclosure.

Abstract: A process and apparatus is disclosed for providing access to the interior of a vacuum deposition chamber in a vacuum deposition apparatus without exposing residues, such as chlorosilane residues, within the chamber to moisture and/or oxygen-containing gases. The process comprises first placing over the upper surface of the vacuum deposition apparatus an enclosure which has a bottom opening large enough to completely cover the top opening to the chamber, and which is capable of being filled with one or more non-reactive gases. One or more non-reactive gases are then flowed into the enclosure to purge moisture and/or oxygen-containing gases from the enclosure. After the enclosure has been mounted on the apparatus and purged by the flow of non-reactive gases therein, the vacuum deposition chamber may be opened, while continuing the flow of non-reactive gases into the enclosure.