Patents by Inventor Norma E. Sosa
Norma E. Sosa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11175281Abstract: A testing system includes a well cover portion, a sensor portion extending from the well cover portion, a sensing surface disposed on the sensor portion, a conducting wire extending through the sensor portion and contacting the sensing surface, a transducer connected to the conducting wire, and a reference electrode extending through the well cover portion.Type: GrantFiled: August 21, 2018Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Sufi Zafar, Norma E. Sosa
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Patent number: 10686090Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.Type: GrantFiled: September 15, 2017Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Cheng-Wei Cheng, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
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Publication number: 20200064336Abstract: A testing system includes a well cover portion, a sensor portion extending from the well cover portion, a sensing surface disposed on the sensor portion, a conducting wire extending through the sensor portion and contacting the sensing surface, a transducer connected to the conducting wire, and a reference electrode extending through the well cover portion.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: SUFI ZAFAR, NORMA E. SOSA
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Patent number: 10352797Abstract: A tunable and resettable shock sensor using a parallel dipole line (PDL) trap system is provided. In one aspect, a shock sensor includes: a PDL trap having a pair of diametric magnets separated from one another by a gap gM, and a diamagnetic rod levitating in between the diametric magnets; and contact pads below the PDL trap, wherein the contact pads are separated from one another by a space that is less than a length l of the diamagnetic rod. A shock monitoring system is also provided that includes a network of the shock sensors, as is a method for shock monitoring using the shock sensors.Type: GrantFiled: October 10, 2017Date of Patent: July 16, 2019Assignee: International Business Machines CorporationInventors: Oki Gunawan, Norma E. Sosa
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Publication number: 20190107452Abstract: A tunable and resettable shock sensor using a parallel dipole line (PDL) trap system is provided. In one aspect, a shock sensor includes: a PDL trap having a pair of diametric magnets separated from one another by a gap gM, and a diamagnetic rod levitating in between the diametric magnets; and contact pads below the PDL trap, wherein the contact pads are separated from one another by a space that is less than a length l of the diamagnetic rod. A shock monitoring system is also provided that includes a network of the shock sensors, as is a method for shock monitoring using the shock sensors.Type: ApplicationFiled: October 10, 2017Publication date: April 11, 2019Inventors: Oki Gunawan, Norma E. Sosa
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Publication number: 20180006180Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.Type: ApplicationFiled: September 15, 2017Publication date: January 4, 2018Inventors: STEPHEN W. BEDELL, CHENG-WEI CHENG, JEEHWAN KIM, DEVENDRA K. SADANA, KUEN-TING SHIU, NORMA E. SOSA CORTES
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Patent number: 9818901Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.Type: GrantFiled: May 13, 2011Date of Patent: November 14, 2017Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Cheng-Wei Cheng, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
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Patent number: 9590054Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.Type: GrantFiled: January 20, 2016Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Alfred Grill, Deborah A. Neumayer, Dae-Gyu Park, Norma E. Sosa, Min Yang
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Publication number: 20160141377Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.Type: ApplicationFiled: January 20, 2016Publication date: May 19, 2016Inventors: Kevin K. Chan, Alfred Grill, Deborah A. Neumayer, Dae-Gyu Park, Norma E. Sosa, Min Yang
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Patent number: 9324564Abstract: Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled.Type: GrantFiled: July 13, 2015Date of Patent: April 26, 2016Assignees: International Business Machines Corporation, KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGYInventors: Ibrahim Alhomoudi, Stephen W. Bedell, Cheng-Wei Cheng, Keith E. Fogel, Devendra K. Sadana, Katherine L. Saenger, Norma E. Sosa, Ning Li
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Patent number: 9293557Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.Type: GrantFiled: July 14, 2014Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Alfred Grill, Deborah A. Neumayer, Dae-Gyu Park, Norma E. Sosa, Min Yang
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Publication number: 20150325443Abstract: Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled.Type: ApplicationFiled: July 13, 2015Publication date: November 12, 2015Inventors: Ibrahim Alhomoudi, Stephen W. Bedell, Cheng-Wei Cheng, Keith E. Fogel, Devendra K. Sadana, Katherine L. Saenger, Norma E. Sosa, Ning Li
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Patent number: 9166161Abstract: A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. A second non-conductive layer is deposited above the first non-conductive layer. A second well is defined by the second non-conductive layer and positioned directly above the first well. A second electrically conductive liner lines at least one wall of the second well such that the second electrically conductive liner is not in physical contact with the first electrically conductive liner. Furthermore, the phase change material is deposited in the second well.Type: GrantFiled: September 19, 2014Date of Patent: October 20, 2015Assignee: GlobalFoundries U.S. 2 LLCInventors: Matthew J. BrightSky, Chung H. Lam, Jing Li, Alejandro G. Schrott, Norma E. Sosa Cortes
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Publication number: 20150236115Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.Type: ApplicationFiled: July 14, 2014Publication date: August 20, 2015Inventors: Kevin K. Chan, Alfred Grill, Deborah A. Neumayer, Dae-Gyu Park, Norma E. Sosa, Min Yang
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Patent number: 9079269Abstract: Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled.Type: GrantFiled: November 22, 2011Date of Patent: July 14, 2015Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Cheng-Wei Cheng, Keith E. Fogel, Devendra K. Sadana, Katherine L. Saenger, Norma E. Sosa Cortes, Ning Li, Ibrahim Alhomoudi
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Patent number: 9059404Abstract: A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element.Type: GrantFiled: August 16, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Matthew J. BrightSky, SangBum Kim, Chung H. Lam, Asit K. Ray, Norma E. Sosa Cortes
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Patent number: 9059073Abstract: A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.Type: GrantFiled: September 5, 2012Date of Patent: June 16, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
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Patent number: 9040392Abstract: A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.Type: GrantFiled: June 15, 2011Date of Patent: May 26, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
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Patent number: 9006700Abstract: A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element.Type: GrantFiled: June 24, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Matthew J. BrightSky, SangBum Kim, Chung H. Lam, Asit K. Ray, Norma E. Sosa Cortes
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Patent number: 8969992Abstract: An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.Type: GrantFiled: March 6, 2014Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Norma E. Sosa Cortes, Wilfried E. Haensch, Steven J. Koester, Devendra K. Sadana, Katherine L. Saenger, Ghavam Shahidi, Davood Shahrjerdi