Abstract: A method for identifying a physical memory(ies) associated with a logical memory(ies) in a memory design can include (a) receiving a generic netlist for the memory design, (b) generating a test mode for the memory using the generic netlist, (c) determining the logical memory(ies); (d) performing a simulation on the test mode for the logical memory(ies); and (e) identifying the physical memory(ies) by tracing chip selects for the physical memory(ies) to the logical memory(ies). The identifying the physical memory(ies) may further include identifying which chip selects are active. The identifying the physical memory(ies) can further include tracing an address and a data pin(s) for the logical memory(ies) in the simulation. The identifying the physical memory(ies) can further include determining an address and a data pin(s) for the logical memory(ies) in the simulation.

Abstract: In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the intermediate level module, making it more likely to meet any specified performance of the intermediate level module and reduce area overhead.

Abstract: Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

Abstract: A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.

Abstract: A method of making a circuitized substrate in which the substrate includes circuit elements having exposed surfaces defined by two thin layers of permanent photoimaged solder mask material which are applied through fine mesh screens. The use of two thin layers assures effective coverage of the material to precisely expose the desired surfaces in high-density circuit patterns. A circuitized substrate assembly and an information handling system adapted for having one or more such assemblies therein are also provided.

Abstract: A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.

Abstract: A method of forming a circuitized substrate utilizing a conductive nub structure for enhanced interconnection integrity by using a joining core layer with copper outer layer on it, and forming thru-holes in the joining layer. Placing conductive adhesive in the thru-hole prior to removing the copper outer layers from the joining core layer creates an adhesive bump on joining core layer that engages a conductive secondary metal nub placed on the circuitized substrate-to-joining layer contact points, thus creating an enhanced connection between the layers.

Abstract: An electrically conductive adhesive (ECA) for repairing electrically conductive pad and trace interconnects and a method of repairing interconnect locations. The method of repairing at least one defect within the area of electrically conductive circuitized substrate traces and pads outside of a pristine center area incorporates an ECA and a forming gas plasma. The ECA contains a mixture of components that allow the adhesive to be adapted to specific requirements. Curing the adhesive results in effective electrical connections being formed between the adhesive and the base pad so that the metallurgies of the conductors and of the ECA are effectively combined to engage and repair the conductor defect.

Abstract: A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.

Abstract: A method of making a circuitized substrate assembly in which two or more subassemblies are aligned and bonded together. The bonding, preferably using lamination, results in effective electrical connections being formed between respective pairs of conductors of the subassemblies in such a manner that the metallurgies of the conductors, and those of an interim metallic solder paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies is forced to flow to engage and surround the conductor coupling, without adversely affecting the electrical connection formed.

Abstract: A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.

Abstract: A method of making a circuitized substrate assembly in which two or more subassemblies are aligned and bonded together. The bonding, preferably using lamination, results in effective electrical connections being formed between respective pairs of conductors of the subassemblies in such a manner that the metallurgies of the conductors, and those of an interim metallic solder paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies is forced to flow to engage and surround the conductor coupling, without adversely affecting the electrical connection formed.

Abstract: A method of making a circuitized substrate in which the substrate includes circuit elements having exposed surfaces defined by two thin layers of permanent photoimaged solder mask material which are applied through fine mesh screens. The use of two thin layers assures effective coverage of the material to precisely expose the desired surfaces in high-density circuit patterns. A circuitized substrate assembly and an information handling system adapted for having one or more such assemblies therein are also provided.

Abstract: A method and apparatus for depositing conductive paste in openings of a circuitized substrate such as a multilayered printed circuit board to produce effective conductive thru-holes capable of being electrically coupled to selected conductive layers of the substrate. The invention comprises using vacuum to draw from the underside of the substrate while substantially simultaneously applying the paste onto the substrate's opposing surface. One example of means for accomplishing such paste application is a squeegee, and in one embodiment, two such squeegees may be used. A porous member is used to engage the substrate's undersurface during the vacuum draw, this member being positioned atop a base vacuum member through which the vacuum is drawn.

Abstract: A method and apparatus for depositing conductive paste in openings of a circuitized substrate such as a multilayered printed circuit board to produce effective conductive thru-holes capable of being electrically coupled to selected conductive layers of the substrate. The invention comprises using vacuum to draw from the underside of the substrate while substantially simultaneously applying the paste onto the substrate's opposing surface. One example of means for accomplishing such paste application is a squeegee, and in one embodiment, two such squeegees may be used. A porous member is used to engage the substrate's undersurface during the vacuum draw, this member being positioned atop a base vacuum member through which the vacuum is drawn.

Abstract: A method of plating a circuit pattern on a substrate to produce a circuitized substrate (e.g., a printed circuit board) in which a dual step metallurgy application process is used in combination with a dual step photo-resist removal process. Thru-holes are also possible, albeit not required.