Abstract: The present invention includes a first input signal circuit to receive pulse signals from a voltage-controlled oscillator (VCO), or some other controllable pulse signal source, and a second input signal circuit to receive pulse signals from a magnetic recording medium, or some pulse signal source, with which the voltage controlled oscillator is to be put in phase synchronization. A correction signal generator circuit is connected to both the input signal circuits to provide a first correction signal in response to a pulse signal from the recording medium and to provide a second correction signal in response to a pulse signal from the VCO. There is a third circuit which monitors how long a correction signal is in effect and if such a correction signal is present for longer than a predetermined time, the third circuit terminates the correction signal to enable a new correction signal to be generated in response to the next one of said input signals to arrive.

Abstract: An error detecting and correcting system implementing the Reed-Solomon (1023, 1006) code having code words whose symbols are elements in the Galois field GF(2.sup.10) generated by either the primitive polynomial x.sup.10 +x.sup.3 +1 or x.sup.10 +x.sup.7 +1. An original data word is encoded to produce a code word w(x) including a first set of checksum symbols appended thereto. Upon retrieval, the data symbols of the receive code word y(x) are encoded by the same encoder that encodes the original data word to produce a second set of checksum symbols. Both sets of checksum symbols are modulo-two summed to produce a residue R(x) from which error syndromes S.sub.i can be computed and thus enable rapid correction of errors in the received code word y(x). The system also monitors the number of non-zero symbols in the residue R(x) in order to avoid unnecessary computation of error syndromes S.sub.

Abstract: In a feedback control system wherein data pulses also establish timing coordination between the data and the processing devices, two delay circuits are provided to extract the synchronized clock pulses from the coded incoming signal. This enables relative digital decoding and ensures a precise data transfer to a computer interface. One of the delay circuits enables a data reconditioner circuit to buffer the data and eliminates data peak shifting. The reconditioned data is provided to a coincident circuit which selectively transfers the data to a computer interface and to a phase difference detector. The other delay circuit provides to the phase difference detector a second input corresponding in time to the coded incoming data pulses. The detector's output generates a DC error voltage which synchronizes a voltage controlled oscillator (VCO). The outputs of the VCO are clock pulses in phase with the coded incoming signals.