Abstract: Methods and apparatus for transmitting signals, the transmitter including a memory storing instructions and a controller configured to execute the instructions to cause the transmitter to determine whether a value of transmitter power is less than a threshold, responsive to a determination that the value of transmitter power is less than the threshold: mix a baseband signal with a first oscillator signal to produce a very-low intermediate frequency (VLIF) signal; mix the VLIF signal with a second oscillator signal to produce a radio frequency (RF) signal, and transmit the RF signal.

Abstract: An example method for enabling coherent reception of a radio signal includes, in some implementations, tuning a radio receiver to a first receiver frequency, generating within the radio receiver a test signal having a first test frequency, and measuring a first phase of the test signal while the radio receiver is tuned to the first receiver frequency. The example method also includes tuning the radio receiver to a second receiver frequency, which is different from the first receiver frequency, measuring a second phase of the test signal while the radio receiver is tuned to the second receiver frequency, and calculating a phase relationship depending on the first and second phases of the test signal. A radio receiver for coherent reception of a radio signal also is disclosed.

Abstract: A method for providing a reference clock signal, comprising: generating, by an oscillator, a first clock signal having a first frequency, the first clock signal being coupled to a frequency synthesizer; generating, by the frequency synthesizer, a second clock signal based on the first clock signal, the second clock signal having a second frequency different from the first frequency; outputting a reference clock signal to one or more components of an electronic device, the reference clock signal being one of the first clock signal or the second clock signal; identifying one or more spurious frequency components; and monitoring the reference clock signal for a presence of the one or more spurious frequency components, the monitoring comprising: in response to determining the presence of at least one of the one or more spurious frequency components, selecting a different one of the first clock signal or the second clock signal to be the reference clock signal.

Abstract: A method for providing a reference clock signal, comprising: generating, by an oscillator, a first clock signal having a first frequency, the first clock signal being coupled to a frequency synthesizer; generating, by the frequency synthesizer, a second clock signal based on the first clock signal, the second clock signal having a second frequency different from the first frequency; outputting a reference clock signal to one or more components of an electronic device, the reference clock signal being one of the first clock signal or the second clock signal; identifying one or more spurious frequency components; and monitoring the reference clock signal for a presence of the one or more spurious frequency components, the monitoring comprising: in response to determining the presence of at least one of the one or more spurious frequency components, selecting a different one of the first clock signal or the second clock signal to be the reference clock signal.

Abstract: Methods and apparatus for transmitting signals, the transmitter including a memory storing instructions and a controller configured to execute the instructions to cause the transmitter to determine whether a value of transmitter power is less than a threshold, responsive to a determination that the value of transmitter power is less than the threshold: mix a baseband signal with a first oscillator signal to produce a very-low intermediate frequency (VLIF) signal; mix the VLIF signal with a second oscillator signal to produce a radio frequency (RF) signal, and transmit the RF signal.

Abstract: A receiver includes one or more mixers configured to sample an input analog signal at a plurality of discrete points in time to obtain a discrete-time sampled signal based on a local oscillating signal provided by a local oscillator; and a sample reordering circuit coupled to the one or more mixers and configured to reorder a sequence of samples received from the one or more mixers.

Abstract: A receiver includes one or more mixers configured to sample an input analog signal at a plurality of discrete points in time to obtain a discrete-time sampled signal based on a local oscillating signal provided by a local oscillator; and a sample reordering circuit coupled to the one or more mixers and configured to reorder a sequence of samples received from the one or more mixers.

Abstract: A receiver includes one or more mixers configured to sample an input analog signal at a plurality of discrete points in time to obtain a discrete-time sampled signal based on a local oscillating signal provided by a local oscillator; and a sample reordering circuit coupled to the one or more mixers and configured to reorder a sequence of samples received from the one or more mixers.

Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.

Abstract: An integrated circuit comprising processing logic for operably coupling to radio frequency (RF) receiver circuitry arranged to receive a wireless network signal. The receiver circuitry generates in-phase and quadrature digital baseband representations of the wireless network signal. The processing logic determines quadrature (I/Q) imbalance of the RF receiver circuitry based on the in-phase and quadrature digital baseband representations of the wireless network signal.

Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.

Abstract: A very low intermediate frequency (VLIF) receiver comprising a first and second mixer circuits, characterised in that receiver comprises a means of estimating the energy in a desired signal band; a means of estimating the energy in a band of frequencies comprising the desired signal band; and a means of altering a VLIF of the receiver according to the ratio of the energy in a desired signal band and the energy in the band of frequencies comprising the desired signal band.

Abstract: A method of communicating between a mobile communication device including a power supply, and a base station. The mobile device has first and second alternative communication modes, the first communication mode having higher quality of service and higher power consumption than the second communication mode. The second communication mode is adopted in response to a characteristic of the mobile device power supply indicative of a reduced reserve of power in the power supply, and a state indication is transmitted from the mobile device to the base station. The base station can respond to the state indication from the mobile device by modifying a communication characteristic of the base station with the mobile device, whereby to tend to compensate for the mobile device switching between the first and second communication modes.

Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto.

Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to generate a synthesized frequency signal from the reference signal. The synthesized frequency generation logic comprises programmable divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period substantially equal to N times that of the reference signal, where N comprises a programmable integer value. The synthesizer frequency generation logic is arranged to generate the synthesized frequency signal comprising a frequency with a period substantially equal to 1/M that of the divided signal, where M comprises a further programmable integer value.

Abstract: A wireless communication unit comprises a transmitter having a power amplifier and a feedback path operably coupled to the power amplifier. The feedback path comprises a coupler for feeding back a portion of a signal to be transmitted and a detector for detecting a power level of the fed back signal. A controller provides a ramp signal to the power amplifier that controls an amplitude characteristic of the signal to be transmitted. Averaging logic is operably coupled to the detector and arranged to average the detected power level over a first period. Comparison logic is operably coupled to the averaging logic and arranged to compare the average detected power level with a reference value. The controller is operably coupled to the comparison logic and arranged to scale a ramp signal applied to the power amplifier in response to the comparison.

Abstract: A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit.

Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.

Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.