Abstract: A differentail amplifier with input gate oxide breakdown avoidance amplifies a difference between two signals while maintaining voltage drops across transistor utilized in the differential amplifier to below a gate oxide breakdown level. A pull up structure added to a traditional differential amplifier allows the circuit to be utilized in IO pads of an integrated circuit and to be composed of thin oxide transistor normally only found in the core circuitry of the integrated circuit and. The pull up structure is composed of three thin oxide transistors, the first transistor is connected in series with the other two, and the other two connected in parallel with respect to each other.

Abstract: A reservation station with format conversion logic enables the implementation of a superscalar computer processing system which incorporates both a floating point functional unit and non-floating point functional units. By converting operand data in a floating point reservation station from external formats to an internal floating point format, a system incorporating such a floating point reservation station enables the representation of operand data in uniform external formats outside floating point arithmetic units (e.g., in a reorder buffer, on operand and result busses, and within non-floating functional units) while also enabling the use of a specialized internal representation (internal floating point format) within floating point arithmetic units.

Abstract: A ring oscillator with differential delay stages employs an automatic gain control circuit producing a gain adjust signal that is responsive to a frequency control voltage applied to the ring oscillator. The effect of the frequency control voltage on the output voltage of the ring oscillator is counterbalanced by the gain adjust signal which prevents the output voltages of the delay stages from varying excessively over frequency. Further, the output stage of the ring oscillator includes shut off circuitry that allows the ring oscillator to be shut off in a non-oscillating mode in which it draws little current.

Abstract: A low power voltage reference circuit is provided, it has a normal operating mode and a low power mode. In the low power mode, a startup circuit is isolated and operates in low power, and the voltage reference portion of the circuit also operates in low power and provides low voltage output. When the circuit is instead enabled, the startup circuitry forced the referenced circuitry out of its low power mode and into a stable, reference mode.

Abstract: A reservation station with format conversion logic enables the implementation of a superscalar computer processing system which incorporates both a floating point functional unit and non-floating point functional units. By converting operand data in a floating point reservation station from external formats to an internal floating point format, a system incorporating such a floating point reservation station enables the representation of operand data in uniform external formats outside floating point arithmetic units (e.g., in a reorder buffer, on operand and result busses, and within non-floating functional units) while also enabling the use of a specialized internal representation (internal floating point format) within floating point arithmetic units.

Abstract: A bus control interface selectively and transparently couples a bus agent to a cache and to a memory to provide transparent burst access to addressable data having a portion residing in cache and a portion residing in memory. The bus control interface steers transactions to the cache or to the memory depending on where the data resides. In this way, the bus control interface supports, without a disconnect, burst read transactions that cross cache line boundaries. The bus control interface also supports bus watching single-word read (and write) transactions as well as burst write transactions.

Abstract: A test-vector generating system (200) controls a processor (110) having a paradigm floating point functional unit (160) which executes a paradigm floating point instruction set. The system includes computer program modules including an interactive test selection process (202) in which a test instruction is selected from the paradigm instruction set, an operand data generation process (222), a test instruction execution process (226) in which the paradigm functional unit executes the test instruction operating upon the generated operand data and a test vector result recording process (208) in which a test vector result of the test instruction execution is recorded.