Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A board game roughly similar to chess, but having unconventional game elements, is shown and described. The identities of all playing pieces except a king are initially concealed, and revealed after making an initial move. The initial move is predetermined, and changes if the revealed identity differs from a corresponding pre-assigned identity. Move characteristics of the playing pieces are varied in most cases from their counterparts in conventional chess. The king may not leave a certain area of the board, and is not permitted to face an opposed king without presence of an intervening playing piece. A new playing piece with unique move requirements is introduced.

Abstract: Apparatus and method of a variation of the game of chess are shown and described. The playing board is conventional. Playing pieces have two exposable faces including an initial face concealing identity of that playing piece, and a subsequently exposed face identifying identity of that playing piece. Initially, all playing pieces occupy conventional starting positions on the board, but with the face concealing identity visible to the players. The king is an exception, and is identified and placed in the conventional position for a king. Initial moves by each playing piece have move characteristics of that playing piece which conventionally occupies its space on the board. Upon completion of a first move, the face identifying identity of the playing piece is exposed. Moves subsequent to the initial moves have move characteristics of playing pieces identified by exposing the identity. The game may then be played according to conventional rules.

Abstract: In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

Abstract: The invention relates to a method and a system (SYS) for managing an alarm signal in a system comprising a first internal clock. The system is intended to cooperate with a portable player (PP) comprising a second internal clock and a screen (S). The method comprises the steps of: —setting the time of said first internal clock at the time of said second internal clock, —selecting a given time value being displayed on said screen, —memorizing said given time value in said system, —setting the time of said second internal clock at the time of said first internal clock, —triggering an alarm signal on said system when the time of said first internal clock reaches said given time value. According to this method, when the portable player is docked to the system, the system according to the invention does not require its own screen because the screen of the portable player is used to display the current time and the alarm time during setting it, resulting in a reduction of the costs of the system.

Abstract: In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

Abstract: The invention relates to a method and a system (SYS) for managing an alarm signal in a system comprising a first internal clock. The system is intended to cooperate with a portable player (PP) comprising a second internal clock and a screen (S). The method comprises the steps of: —setting the time of said first internal clock at the time of said second internal clock, —selecting a given time value being displayed on said screen, —memorizing said given time value in said system, —setting the time of said second internal clock at the time of said first internal clock, —triggering an alarm signal on said system when the time of said first internal clock reaches said given time value. According to this method, when the portable player is docked to the system, the system according to the invention does not require its own screen because the screen of the portable player is used to display the current time and the alarm time during setting it, resulting in a reduction of the costs of the system.

Abstract: In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a viral entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame"s destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.