Patents by Inventor Norman Chen
Norman Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160093565Abstract: Methods for forming a semiconductor layer, such as a metal 1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.Type: ApplicationFiled: November 30, 2015Publication date: March 31, 2016Inventors: Sonia GHOSH, Randy MANN, Norman CHEN, Shaowen GAO
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Patent number: 9263349Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.Type: GrantFiled: November 8, 2013Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sonia Ghosh, Randy Mann, Norman Chen, Shaowen Gao
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Patent number: 9171735Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.Type: GrantFiled: February 15, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Sohan Mehta, Norman Chen, Yuyang Sun, Matthew Herrick, Shyam Pal, Jeong Soo Kim
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Patent number: 9091923Abstract: Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators (“PAGs”) and photobase generators (“PBGs”), is described.Type: GrantFiled: February 22, 2007Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Vencent Chang, Norman Chen, Kuei Shun Chen, Chin-Hsiang Lin
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Patent number: 9064086Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.Type: GrantFiled: October 28, 2014Date of Patent: June 23, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Chidam Kallingal, Norman Chen
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Publication number: 20150130026Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Sonia GHOSH, Randy MANN, Norman CHEN, Shaowen GAO
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Patent number: 9026977Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.Type: GrantFiled: August 16, 2013Date of Patent: May 5, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Marc Tarabbia, Norman Chen, Jian Liu, Nader Magdy Hindawy, Tuhin Guha Neogi, Mahbub Rashed, Anurag Mittal
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Publication number: 20150052494Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Marc TARABBIA, Norman CHEN, Jian LIU, Nader Magdy HINDAWY, Tuhin Guha NEOGI, Mahbub RASHED, Anurag MITTAL
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Publication number: 20150046887Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Yuyang Sun, Chidam Kallingal, Norman Chen
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Patent number: 8910094Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.Type: GrantFiled: February 6, 2013Date of Patent: December 9, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Chidam Kallingal, Norman Chen
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Publication number: 20140235055Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Sohan Mehta, Norman Chen, Yuyang Sun, Matthew Herrick, Shyam Pal, Jeong Soo Kim
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Publication number: 20140223390Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.Type: ApplicationFiled: February 6, 2013Publication date: August 7, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Yuyang Sun, Chidam Kallingal, Norman Chen
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Patent number: 8612904Abstract: Embodiments of the invention provide approaches for optimizing illumination and polarization for advanced optical lithography. Specifically, an illumination pupil plane of an illumination source is bisected into a plurality of elements. Preferred elements of the illumination pupil plane are selected for a set of integrated circuit (IC) design features. An imaging performance of the set of IC design features for the preferred elements is evaluated at different polarization states to determine an optimal illumination and polarization condition for each IC design feature. Imaging performance of the combined IC design features, evaluated at various optimal illumination and polarization outcomes synthesized at different intensity ratios, is reviewed against a set of design tolerance requirements to finalize optical illumination and polarization conditions for the entire IC design.Type: GrantFiled: November 21, 2012Date of Patent: December 17, 2013Assignee: GLOBAL FOUNDRIES Inc.Inventors: Chang A. Wang, Norman Chen, Chidam Kallingal
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Publication number: 20130286371Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: George Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin
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Patent number: 8472005Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.Type: GrantFiled: February 22, 2007Date of Patent: June 25, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin
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Patent number: 7838205Abstract: Photolithography processing methods by which a photoresist layer is deposited, a portion of the photoresist layer is exposed to electromagnetic radiation to transfer a reticle pattern thereto, and the exposed portion of the photoresist layer is treated with thermal energy while being subjected to an electric field, wherein the electric field is configured to substantially limit diffusion of the exposed photoresist layer portion to anisotropic diffusion.Type: GrantFiled: July 7, 2006Date of Patent: November 23, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Vincent Chang, Kuei Shun Chen, George Liu, Norman Chen
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Patent number: 7642101Abstract: A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.Type: GrantFiled: December 5, 2006Date of Patent: January 5, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Vencent Chang, Chin-Hsiang Lin, Kuei Shun Chen, Norman Chen
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Patent number: 7432042Abstract: An immersion lithography process is described as follows. A photoresist layer and a protective layer are sequentially formed on a material layer, and then an immersion exposure step is performed to define an exposed portion and an unexposed portion in the photoresist layer. A solubilization step is conducted to solubilize the protective layer on the exposed portion of the photoresist layer, and then a development step is conducted to remove the exposed portion of the photoresist layer and the protective layer thereon. Since the photoresist layer is covered with the protective layer, the chemicals in the photoresist layer do not diffuse into the immersion liquid to cause contamination. The protective layer can be patterned simultaneously in the development step, and no extra step is required to remove the protective layer. Therefore, the whole lithography process is not complicated.Type: GrantFiled: December 3, 2003Date of Patent: October 7, 2008Assignee: United Microelectronics Corp.Inventors: Vencent Chang, George Liu, Norman Chen
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Publication number: 20080206679Abstract: Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators (“PAGs”) and photobase generators (“PBGs”), is described.Type: ApplicationFiled: February 22, 2007Publication date: August 28, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Vencent Chang, Norman Chen, Kuei Shun Chen, Chin-Hsiang Lin
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Publication number: 20080204688Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.Type: ApplicationFiled: February 22, 2007Publication date: August 28, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin