Patents by Inventor Norman E. Mause

Norman E. Mause has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of generating a schematic driven layout for a hierarchical integrated circuit design
    Patent number: 7082589
    Abstract: A method of generating a schematic driven layout for an integrated circuit design includes steps of: (a) receiving as input a representation of a integrated circuit design comprising a hierarchy of blocks; (b) selecting a block in the hierarchy of blocks that requires a physical design and that contains no missing components; (c) generating a physical design for the selected block so that the selected block is no longer a missing component of any other block; and (d) repeating steps (b) and (c) until a physical design has been generated for each block in the hierarchy of blocks.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Saunders, Norman E. Mause, C. Chip Brewster