Abstract: An instantaneous context switching speech recognition system is disclosed which enables a speech recognition application to be changed without loading new pattern matching data into the system. Selectable pointer maps are included in the memory of the system which selectively change the relationship between words and phonemes between a first application context and the pattern matching logic to a second application context and the pattern matching logic.

Abstract: A telephony channel simulation process is disclosed for training a speech recognizer to respond to speech obtained from telephone systems. An input speech data set is provided to a speech recognition training processor, whose bandwidth is higher than a telephone bandwidth. The process performs a series of alterations to the input speech data set to obtain a modified speech data set. The modified speech data set enables the speech recognition processor to perform speech recognition on voice signals from a telephone system.

Abstract: A system is disclosed to provide X.21 in-band call establishment signaling in the data path of a data communication system by utilizing a data port, digital switch and telephone signaling call processor in a satellite communications controller. The system includes an X.21 signaling protocol between a DTE and the satellite communications controller on the terrestrial side and allows self-switched digital data port functions in lieu of associated voice port and line functions as practiced in the prior art. An important aspect is that the signaling rate is the same as the line data rate. The data port goes through three generalized states during a normal call process. The first general state is idle, the second general state is the signaling state and the third general state is the data transfer state. At the start of the signaling state, the E input to the call processor is activated for the appropriate port. Call establishment signals are then processed through the digital switch and an X.

Abstract: An improved system for identifying and compacting text data to be transmitted over communications lines and thereby reducing the data volume and transmission time. Transmitting and receiving text processing systems are provided identical library memories containing words commonly used in correspondence. Each word in a document to be communicated is compared to the transmitting system's word library and, if found in the library, only the library address is transmitted. If the word is not found in the library, then it is added to the transmitting system's library, sent, and added to the receiving system's library. The receiving system reconstructs the document by using the received addresses to access the appropriate words from its library and place them in the document. The system combines this word match encoding with character match encoding and facsimile run length encoding for communicating words not found in the system library.

Abstract: A method and system for compacting text data to be transmitted over communications lines and thereby reduce the data volume and transmission time. Transmitting and receiving text processing systems are provided identical library memories containing text strings such as words commonly used in correspondence. Each word in a document to be communicated is compared to the transmitting system's word library and, if found in the library, only the library address is transmitted. If the word is not found in the library, then it is added to the transmitting system's library, sent, and added to the receiving system's library. The receiving system reconstructs the document by using the received addresses to access the appropriate words from its library and place them in the document. The system combines this word match encoding with character match encoding and facsimile run length encoding for communicating words not found in the system library.

Abstract: A control architecture is disclosed for a communications controller, for connecting a control processor in the communications controller to a plurality of internal processing subunits which operate asynchronously at different data rates. The architecture includes a control adapter which is connected between the control processor and a common subunit bus, for receiving from the control processor, a control command, a plurality of data words, and an associated address for a respective one of the processing subunits. The control adapter outputs an operating code and the plurality of data words on the common subunit bus and further outputs a subunit select signal on a respective subunit select line to the subunit designated in the address. The adapter further includes a memory for storing the number of shift intervals to be applied to a stack shift signal which is output on a stack shift bus which is common to all of the subunits.

Abstract: The transmission and reception pattern generators are synchronized for all data ports operating at the same data rate throughout an entire TDMA system. This eliminates the necessity for bit stuffing to accommodate non-integral multiple data rate data ports and yet allows data activity compression operations to be carried out.

Abstract: The invention finds application in a TDMA communications controller having a plurality of i input/output ports. The input/output ports transfer data from respective, local data users to a transmit bus and transfer data from a receive bus to respective local users on a time interleaved basis during periodic TDMA frames. Each port operates at its own data rate R.sub.i, with data ports having different data rates in the controller. The invention includes a test card which has a read-only memory (ROM) for storing test patterns for each of the data rates R.sub.i. The test card further includes a random access memory (RAM) having an input connected to the ROM, for storing one of the test patterns from the ROM. The test card further includes a processor having control outputs to the RAM and the ROM for controlling the transfer of one of the test patterns from the ROM to the RAM for the data rate R.sub.j of the data port under test.

Abstract: A call processor is disclosed for a satellite communications controller, having a plurality of M voice ports, with an E lead input and an M lead output connected to each of a first subplurality of voice ports for rotary dial telephones, a tone digit interface connected to each of a second subplurality of voice ports which are dedicated to transducing a tone digit received from a multifrequency dialing telephone which is connected to one of a third plurality of voice ports. The third voice ports are connected by means of an intranodal wrap through a digital switch in the communications controller with the transducing circuits at the second voice ports so that the transducing circuitry can be shared among all of the third plurality of voice ports connected to multifrequency dialing telephones. The call processor employs a substantial amount of processing logic in the form of clocked control logic which is executed in a nested time slice operation.