Patents by Inventor Norman J. Rasmussen
Norman J. Rasmussen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6594717Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.Type: GrantFiled: September 9, 2002Date of Patent: July 15, 2003Assignee: Intel CorporationInventors: Norman J. Rasmussen, Brad W. Hosler, Darren Abramson, Michael J. McTague
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Publication number: 20030065829Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.Type: ApplicationFiled: September 9, 2002Publication date: April 3, 2003Inventors: Norman J. Rasmussen, Brad W. Hosler, Darren Abramson, Michael J. McTague
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Patent number: 6502146Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.Type: GrantFiled: March 29, 2000Date of Patent: December 31, 2002Assignee: Intel CorporationInventors: Norman J. Rasmussen, Brad W. Hosler, Darren Abramson, Michael J. McTague
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Patent number: 6434692Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.Type: GrantFiled: February 23, 2001Date of Patent: August 13, 2002Assignee: Intel CorporationInventors: Norman J. Rasmussen, William S. Wu
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Patent number: 6317803Abstract: A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.Type: GrantFiled: September 27, 1996Date of Patent: November 13, 2001Assignee: Intel CorporationInventors: Norman J. Rasmussen, Gary A. Solomon, David G. Carson, George R. Hayek, Brent S. Baxter, Colyn Case
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Patent number: 6266719Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.Type: GrantFiled: September 6, 2000Date of Patent: July 24, 2001Assignee: Intel CorporationInventors: Norman J. Rasmussen, William S. Wu
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Publication number: 20010007999Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.Type: ApplicationFiled: February 23, 2001Publication date: July 12, 2001Inventors: Norman J. Rasmussen, William S. Wu
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Patent number: 6167468Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.Type: GrantFiled: August 25, 1999Date of Patent: December 26, 2000Assignee: Intel CorporationInventors: Norman J. Rasmussen, William S. Wu
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Patent number: 6112016Abstract: Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented.Type: GrantFiled: March 27, 1997Date of Patent: August 29, 2000Assignee: Intel CorporationInventors: Peter D. MacWilliams, Norman J. Rasmussen, Nicholas D. Wade, William S. F. Wu
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Patent number: 6047355Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.Type: GrantFiled: March 10, 1997Date of Patent: April 4, 2000Assignee: Intel CorporationInventors: William S. Wu, Norman J. Rasmussen, Suresh K. Marisetty, Puthiya K. Nizar
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Patent number: 6006291Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.Type: GrantFiled: December 31, 1997Date of Patent: December 21, 1999Assignee: Intel CorporationInventors: Norman J. Rasmussen, William S. Wu
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Patent number: 5948094Abstract: A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent is granted to that bus agent for executing a transaction. A timer is started and the transaction is executed. If the timer does not expire before the transaction is completed, another request from that same bus agent is granted to the bus agent for executing an additional transaction before a subsequent arbitration event is initiated.Type: GrantFiled: September 17, 1997Date of Patent: September 7, 1999Assignee: Intel CorporationInventors: Gary A. Solomon, Norman J. Rasmussen, Peter D. MacWilliams
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Patent number: 5822767Abstract: Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented.Type: GrantFiled: March 27, 1997Date of Patent: October 13, 1998Assignee: Intel CorporationInventors: Peter D. MacWilliams, Norman J. Rasmussen, Nicholas D. Wade, William S. F. Wu
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Patent number: 5809340Abstract: Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.Type: GrantFiled: August 12, 1997Date of Patent: September 15, 1998Assignee: Packard Bell NECInventors: James F. Bertone, Bruno DiPlacido, Jr., Thomas F. Joyce, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr., Chester M. Nibby, Jr., Michelle A. Pence, Marc Sanfacon, Jian-Kuo Shen, Jeffrey S. Somers, G. Lewis Steiner, William S. Wu, Norman J. Rasmussen, Suresh K. Marisetty, Puthiya K. Nizar
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Patent number: 5651137Abstract: Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented.Type: GrantFiled: April 12, 1995Date of Patent: July 22, 1997Assignee: Intel CorporationInventors: Peter D. MacWilliams, Norman J. Rasmussen, Nicholas D. Wade, William S. F. Wu
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Patent number: 5522069Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.Type: GrantFiled: June 10, 1994Date of Patent: May 28, 1996Assignee: Zenith Data Systems CorporationInventors: James F. Bertone, Bruno DiPlacido, Jr., Thomas F. Joyce, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr., Chester M. Nibby, Jr., Michelle A. Pence, Marc Sanfacon, Jian-Kuo Shen, Jeffrey S. Somers, G. Lewis Steiner, William S. Wu, Norman J. Rasmussen, Suresh K. Marisetty, Puthiya K. Nizar