Abstract: A rack is provided. In one aspect, a rack includes a horizontal tray, a vertical tray, and an L-shaped cable cartridge. The L-shaped cable cartridge includes connectors configured to connect to horizontal tray connectors on a first side of the horizontal tray and to vertical tray connectors on a second side of the vertical tray that is orthogonal to the first side. Further, the L-shaped cable cartridge includes cables connected to the connectors in the L-shaped cable cartridge to facilitate communication between the horizontal and vertical trays.

Abstract: A system and method is provided for improving integrated circuit device characterization without requiring external tester hardware. On-chip circuitry is provided to measure the delay of a signal through a given scan chain when the scan chain latches have been placed in flush mode. A control signal generated by the on-chip circuitry simultaneously generates a timing measurement signal as well as initiates a counter/timer to count/time the amount of time it takes for the timing measurement signal to pass through certain operational circuitry of the integrated circuit device. The resolution of the measurement is the resolution of the integrated circuit device's global clock.

Abstract: A digitally tunable low voltage CMOS current reference is disclosed. A tunable current reference circuit is provided that includes a current source circuit that is coupled to a power supply voltage. The current source circuit provides a stable current reference output regardless of fluctuations in the power supply voltage. Multiple digitally selectable inputs are included in the current reference circuit and are coupled to the current source circuit. These inputs are used to adjust a value of the current reference output.

Abstract: A system and method for performing functional verification of a device, and in particular a technique for performing phase-locked loop (PLL) functional verification by the device which contains the PLL circuitry. A relatively slow-speed external clock is provided to the device, and is used to generate control signals to a counter. PLL circuitry within the device generates a relatively high-speed master clock signal for use by the device. This master clock signal is coupled to a clock input of the counter, the counter having various control inputs that are used to selectively count clock pulses of the master clock. As the frequency of the external clock signal is known, and the master clock signal is generated from known PLL circuitry, it is possible to analyze the count value from the counter to determine whether the PLL circuitry used to generate the master clock is operating properly.

Abstract: An apparatus and method for accurately tuning the speed of an integrated circuit, i.e. a computer chip, using a built-in sense circuit and controller are provided. The sense circuit is provided in association with a monitored path. The sense circuit includes a variable delay element coupled to a controller. A data signal from the monitored path is provided to the sense circuit which adds an amount of delay as determined by the controller to the data signal. The delayed data signal and the original data signal are compared to determine if their values match. If they match, then the amount of delay added by the variable delay element is increased. If they do not match, then a previous amount of delay, prior to the mismatch, is output as the slack of the monitored path. The slack may then be used to tune the speed of the integrated circuit.

Abstract: A mechanism is provided to address a structure under test and to identify a point of failure. A test open line carries a signal that indicates whether a structure under test is open or closed. A test short line carries a signal that indicates whether a structure under test is shorted. A test structure may include an array of cells, where each cell includes a circuit including structures to test. The cells may be scanned using scan only latches and signals on the test open and/or test short lines may be recorded. A test circuit may include a digital mode and an analog mode. The digital mode provides an open or closed value. The analog mode includes a programmable load. The output of the analog mode provides a resistance value that is relative to the programmable load.

Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

Abstract: A portable toothbrush assembly is provided in which a toothbrush and mouth care solution dispenser are sealed within an outer bag. The dispenser preferably is constantly oriented above the bristles of the toothbrush until use. While remaining sealed within the outer bag, the dispenser can be squeezed in order to rupture the dispenser and distribute mouth care solution over the bristles of the toothbrush. The outer bag can then be opened, exposing the toothbrush for use and then, if desired, disposal.