Abstract: A selection circuit. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A design structure and method. The design structure comprises a selection circuit comprising a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A design structure and method comprising a degradation detection circuit configured to respond to degradation. The degradation detection circuit is located within a semiconductor device and comprises a process sensitive circuit, a measurement circuit, a calculation circuit, and a control circuit. The method comprises subjecting the semiconductor device to a first operating condition. A first value at a first time for a parameter of the process sensitive circuit is measured by the measurement circuit. The semiconductor device is operated to perform an intended function. A second value at a second time for the parameter of the circuit is measured by the measurement circuit. The second time is different from the first time. A first differential value between the first value and the second value is determined by the calculation circuit. The control circuit is configured to receive an enable signal.

Abstract: A design structure and method. The design structure comprises a selection circuit comprising a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A design structure and method comprising a degradation detection circuit configured to respond to degradation. The degradation detection circuit is located within a semiconductor device and comprises a process sensitive circuit, a measurement circuit, a calculation circuit, and a control circuit. The method comprises subjecting the semiconductor device to a first operating condition. A first value at a first time for a parameter of the process sensitive circuit is measured by the measurement circuit. The semiconductor device is operated to perform an intended function. A second value at a second time for the parameter of the circuit is measured by the measurement circuit. The second time is different from the first time. A first differential value between the first value and the second value is determined by the calculation circuit. The control circuit is configured to receive an enable signal.

Abstract: A selection circuit. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A selection circuit and method. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A selection circuit and method. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A degradation detection method and circuit system for responding to degradation. The circuit system is located within a semiconductor device and comprises a process sensitive circuit, a measurement circuit, and a calculation circuit. The method comprises subjecting the semiconductor device to a first operating condition. A first value at a first time for a parameter of the process sensitive circuit is measured by the measurement circuit. The semiconductor device is operated to perform an intended function. A second value at a second time for the parameter of the circuit is measured by the measurement circuit. The second time is different from the first time. A first differential value between the first value and the second value is determined by the calculation circuit.

Abstract: A neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit is disclosed. The neuron circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transistors, and the body of one of the three transistors is controlled by a weighted input. The neuron body circuit block includes a current mirror circuit, a summing circuit, and an invertor circuit. The neuron body circuit is coupled to the synapse circuit block to generate an output pulse.

Abstract: A neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit is disclosed. The neuron circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transistors, and the body of one of the three transistors is controlled by a weighted input. The neuron body circuit block includes a current mirror circuit, a summing circuit, and an invertor circuit. The neuron body circuit is coupled to the synapse circuit block to generate an output pulse.

Abstract: A method and structure for designing a circuit, including identifying paths in the circuit not satisfying a preselected performance criteria, wherein identified paths are initially designed to be coupled to a first power supply, and redesigning the circuit such that the identified paths are coupled to a second power supply having a higher voltage than the first power supply. The higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.

Abstract: A method and structure for designing a circuit, including identifying paths in the circuit not satisfying a preselected performance criteria, wherein identified paths are initially designed to be coupled to a first power supply, and redesigning the circuit such that the identified paths are coupled to a second power supply having a higher voltage than the first power supply. The higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.

Abstract: A ratio-logic system having an input sensing device and a resetable delay device is disclosed. The input sensing device receives an input having a first logic state and a second input having a second logic state. The input sensing device then asynchronously outputs a first state-change signal if the first logic state differs from the logic state of a previous input, and a second state-change signal if the second logic state differs from the first logic state. The resetable delay device receives the first and second state-change signals and asynchronously outputs a power-up signal to a ratio-logic device for a predetermined amount of time after the first state-change signal is received. The resetable delay device then powers-down the ratio-logic device after the predetermined amount of time is over. The predetermined amount of time is reset if the input sensing device receives the second state-change signal before the predetermined amount of time is over.