Patents by Inventor Norman K. James
Norman K. James has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9627012Abstract: Aspects include a computer-implemented method for scanning data into a shift register. The method includes receiving, by a circuit, a data signal, wherein the data signal propagates in a first direction; and receiving, by the circuit, a clock signal, wherein the clock signal propagates in a second direction, wherein the second direction is in a reverse direction of the first direction.Type: GrantFiled: June 29, 2016Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William V. Huott, Norman K. James, Pradip Patel, Daniel Rodko
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Patent number: 9584597Abstract: A computing node includes at least one hardware layer comprising a plurality of hardware resources and at least one virtualization layer operative to manage at one virtual machine defined by at least one resource from among the plurality of hardware resources. The computing node includes load balancing interrupt logic configured in the hardware layer of the node. The load balancing interrupt logic is operative to compare at least one resource utilization level of the plurality of hardware resources by the at least one virtual machine with at least one threshold. The load balancing interrupt logic is operative to generate at least one load balancing interrupt indicating at least one load balancing status of the computing node based on the comparison of the at least one resource utilization level with the at least one threshold.Type: GrantFiled: March 18, 2016Date of Patent: February 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norman K. James, Benjamin C. Nowak, Mark W. Vanderwiele
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Publication number: 20160205181Abstract: A computing node includes at least one hardware layer comprising a plurality of hardware resources and at least one virtualization layer operative to manage at one virtual machine defined by at least one resource from among the plurality of hardware resources. The computing node includes load balancing interrupt logic configured in the hardware layer of the node. The load balancing interrupt logic is operative to compare at least one resource utilization level of the plurality of hardware resources by the at least one virtual machine with at least one threshold. The load balancing interrupt logic is operative to generate at least one load balancing interrupt indicating at least one load balancing status of the computing node based on the comparison of the at least one resource utilization level with the at least one threshold.Type: ApplicationFiled: March 18, 2016Publication date: July 14, 2016Inventors: NORMAN K. JAMES, BENJAMIN C. NOWAK, MARK W. VANDERWIELE
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Patent number: 9294557Abstract: A computing node includes at least one hardware layer comprising a plurality of hardware resources and at least one virtualization layer operative to manage at one virtual machine defined by at least one resource from among the plurality of hardware resources. The computing node includes load balancing interrupt logic configured in the hardware layer of the node. The load balancing interrupt logic is operative to compare at least one resource utilization level of the plurality of hardware resources by the at least one virtual machine with at least one threshold. The load balancing interrupt logic is operative to generate at least one load balancing interrupt indicating at least one load balancing status of the computing node based on the comparison of the at least one resource utilization level with the at least one threshold.Type: GrantFiled: April 19, 2013Date of Patent: March 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norman K. James, Benjamin C. Nowak, Mark W. Vanderwiele
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Publication number: 20140317265Abstract: A computing node includes at least one hardware layer comprising a plurality of hardware resources and at least one virtualization layer operative to manage at one virtual machine defined by at least one resource from among the plurality of hardware resources. The computing node includes load balancing interrupt logic configured in the hardware layer of the node. The load balancing interrupt logic is operative to compare at least one resource utilization level of the plurality of hardware resources by the at least one virtual machine with at least one threshold. The load balancing interrupt logic is operative to generate at least one load balancing interrupt indicating at least one load balancing status of the computing node based on the comparison of the at least one resource utilization level with the at least one threshold.Type: ApplicationFiled: April 19, 2013Publication date: October 23, 2014Inventors: NORMAN K. JAMES, BENJAMIN C. NOWAK, MARK W. VANDERWIELE
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Patent number: 8812879Abstract: A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.Type: GrantFiled: December 30, 2009Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Huajun Wen, Joshua D. Friedrich, Norman K. James, Seongwon Kim, John R. Ripley, Edmund J. Sprogis
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Patent number: 8635478Abstract: During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.Type: GrantFiled: December 29, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Harold W. Chase, Joshua D. Friedrich, Andrew J. Geissler, Soraya Ghiasi, Norman K. James, Jagat V. Pokala, Malcolm S. Ware
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Publication number: 20120198255Abstract: During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.Type: ApplicationFiled: December 29, 2011Publication date: August 2, 2012Applicant: International Business Machines CorporationInventors: Harold W. Chase, Joshua D. Friedrich, Andrew J. Geissler, Soraya Ghiasi, Norman K. James, Jagat V. Pokala, Malcolm S. Ware
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Patent number: 8140902Abstract: A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.Type: GrantFiled: November 12, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Michael S. Floyd, Robert B. Gass, Norman K. James
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Patent number: 8122312Abstract: A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.Type: GrantFiled: April 14, 2009Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Michael S. Floyd, Joshua D. Friedrich, Robert B. Gass, Norman K. James
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Publication number: 20110161682Abstract: A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: International Business Machines CorporationInventors: Huajun Wen, Joshua D. Friedrich, Norman K. James, Seongwon Kim, John R. Ripley, Edmund J. Sprogis
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Publication number: 20100262879Abstract: A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Michael S. Floyd, Joshua D. Friedrich, Robert B. Gass, Norman K. James
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Publication number: 20100122116Abstract: A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.Type: ApplicationFiled: November 12, 2008Publication date: May 13, 2010Applicant: International Business Machines CorporationInventors: Michael S. Floyd, Robert B. Gass, Norman K. James
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Publication number: 20100094572Abstract: Methods, apparatus, and computer program products are described for dynamic frequency and voltage scaling for a computer processor, including identifying during manufacture a nominal operating point of frequency and voltage for a computer processor, the nominal operating point including a nominal operating voltage identified for a design nominal operating frequency; determining, in dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function; and storing, in non-volatile storage on the computer processor during manufacture, information specifying the nominal operating point and the operating range.Type: ApplicationFiled: October 15, 2008Publication date: April 15, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold W. Chase, Joshua D. Friedrich, Soraya Ghiasi, Norman K. James, Jagat V. Pokala
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Patent number: 7576569Abstract: A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).Type: GrantFiled: October 13, 2006Date of Patent: August 18, 2009Assignee: International Business Machines CorporationInventors: Gary D. Carpenter, Alan J. Drake, Harmander S. Deogun, Michael S. Floyd, Norman K. James, Robert M. Senger
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Patent number: 7514947Abstract: A method of and a system for testing semiconductor devices heat a plurality of devices to a burn-in temperature, and perform functional tests in parallel on the plurality of devices at the burn-in temperature. Systems include a burn-in oven and a test multiplexer. The burn-in oven is adapted to receive and heat the devices to the burn-in temperature. The test multiplexer is adapted to apply functional test signals to and receive output signals from the devices in the burn-in oven.Type: GrantFiled: August 31, 2007Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Jason T. Albert, William T. Bronk, Timothy J. Eby, Michael J. Hamilton, Norman K. James
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Publication number: 20090058450Abstract: A method of and a system for testing semiconductor devices heat a plurality of devices to a burn-in temperature, and perform functional tests in parallel on the plurality of devices at the burn-in temperature. Systems include a burn-in oven and a test multiplexer. The burn-in oven is adapted to receive and heat the devices to the burn-in temperature. The test multiplexer is adapted to apply functional test signals to and receive output signals from the devices in the burn-in oven.Type: ApplicationFiled: August 31, 2007Publication date: March 5, 2009Inventors: Jason T. Albert, William T. Bronk, Timothy J. Eby, Michael J. Hamilton, Norman K. James
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Publication number: 20080198700Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.Type: ApplicationFiled: March 10, 2008Publication date: August 21, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
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Publication number: 20080198699Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.Type: ApplicationFiled: March 10, 2008Publication date: August 21, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
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Patent number: 7400555Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.Type: GrantFiled: November 13, 2003Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan