Abstract: A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

Abstract: A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

Abstract: A JFET current mirror is employed in the voltage level shifting section of an operational amplifier. The JFET current mirror includes a first and second JFET coupled at their gates for conducting current I1 and I2 respectively. The gate of a third JFET is connected to the drain of the first JFET and the source of the third JFET is connected by a plurality of diodes to the gate of the first JFET. Current flowing through the diodes produces a voltage drop across the diodes sufficient to bias the first JFET into saturation so that I2 will track I1. A fixed resistance R in the path of I2 produces a predetermined voltage level shift provided that I1 is constant. Therefore, a voltage applied to one terminal of R is level shifted by a predetermined voltage with respect to the other terminal of R. The voltage shifted output is then coupled to an internal amplifier section and the output buffer section of the operational amplifier.

Abstract: An FET amplifier having a current bleeder includes a positive feedback path for increasing the overall gain of the device. The positive feedback path includes an additional FET having its drain source path connected to the current bleeder and its gate connected to the output of the amplifier. The positive feedback causes the current through the current bleeder to vary in direct response to the output of the amplifier, thereby significantly increasing its overall gain.