Abstract: A system for manufacturing a tower structure of a wind turbine includes an additive printing device having a central frame structure with a platform and an arm member. The arm member is generally parallel to a longitudinal axis of the tower structure. The additive printing device also includes a plurality of robotic arms secured to the arm member of the central frame structure. Each of the robotic arms includes a printer head for additively printing one or more materials. The additive printing device further includes at least one nozzle configured for dispensing a cementitious material. Moreover, the system includes one or more molds additively printed via the additive printing device of a polymer material. As such, the mold(s) define inner and outer wall limits of the tower structure.

Abstract: An additive printing device and a method for using the same to manufacture a tower structure of a wind turbine is provided. The additive printing device includes a vertical support structure, a support ring suspended from the vertical support structure, and a printer head movably coupled to the support ring for selectively depositing cementitious material. A drive mechanism, such as a rack and pinion, moves the printer head around the support ring while selectively depositing cementitious material. The vertical support structure may be raised and/or the relative position between the vertical support structure and the printer head may be adjusted to raise the printer head to print subsequent layers. This process may be repeated to print the tower structure layer-by-layer from the ground up.

Abstract: A composite and method for producing the composite by incorporating wood or wood pulp fibres with a suitable thermoplastic polymer and coupling agent are described. Homogeneous, void-free transparent/translucent thermoplastic materials in the form of pellets, films or three-dimensional moldable products are produced. The wood pulp fibres can be discrete natural fibres, and flexible assemblies of nano to micro elements, e.g., assemblies of aggregated carbon nanotubes. It is also possible to use our vacuum-assisted co-extrusion process to produce hybrid composites comprising the wood pulp fibre and a further rigid fibre, like glass or carbon fibres, and a flexible fibre or fibrillar network, like cellulose fibres or cellulose filaments. The thermoplastic resin can be, but not limited to, polyolefins, like polypropylene or polyethylene, or polyesters, like polylactic acid, or co-polymers, like acrylonitrile-butadiene-styrene terpolymer.

Abstract: An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.

Abstract: Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.

Abstract: An exemplary fuse control arrangement can be provided, which can include, for example, a fuse control unit(s), which includes a test access method interface(s) and a programmable memory(ies), wherein the fuse control unit(s) is configured to provide fuse information to repair a memory(ies). The fuse control unit(s) can be coupled to the memory(ies) and the memory(ies) can be coupled to a register repair unit(s). The fuse control unit(s) can provide the register repair unit(s) with the fuse information to repair the memory(ies).

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a two-pass diagnostic test of the target memory, wherein, in the first pass, a data compare unit provides clock cycle values associated with detected mis-compares to a tester, and, in the second pass, the data compare unit extracts data vectors associated with the clock cycle values. Embodiments further provide for a bit fail map report that is generated based on the extracted data vectors.

Abstract: An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).

Abstract: Computer system for programmable built-in self-test (PMBIST) insertion into system-on-chip designs comprising one or more memories, including at least one processor and computer-executable instructions that cause the system to determine a PMBIST configuration based on one or more test configuration files; generate one or more package files based on the PMBIST configuration; insert PMBIST hardware into the SoC design based on the package files and characteristics of the memories; suspend PMBIST hardware insertion after an event related to the package files; and resume PMBIST hardware insertion after receiving one or more updated package files. In some embodiments, the package files are independent of vendor-specific memory models. In some embodiments, the package files comprise a plurality of data structures. Exemplary methods and computer-readable media can also be provided embodying one or more procedures the system is configured to perform.

Abstract: An exemplary bitmap file can be provided, which can include, for example, a map of a cell array structure of a memory(ies), a plurality of memory values superimposed on the cell array structure based on a simulated testing of the memory(ies). The memory values may be values being written to the memory(ies) while the memory(ies) is being tested. The memory values may be values in a test pattern(s) being used to test the memory(ies). Each cell in the cell array structure can have a particular memory value superimposed thereon. A cell(s) in the cell array structure may be highlighted, which may correspond to an incorrect memory value.

Abstract: An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).

Abstract: A composite and method for producing the composite by incorporating wood or wood pulp fibres with a suitable thermoplastic polymer and coupling agent are described. Homogeneous, void-free transparent/translucent thermoplastic materials in the form of pellets, films or three-dimensional moldable products are produced. The wood pulp fibres can be discrete natural fibres, and flexible assemblies of nano to micro elements, e.g., assemblies of aggregated carbon nanotubes. It is also possible to use our vacuum-assisted co-extrusion process to produce hybrid composites comprising the wood pulp fibre and a further rigid fibre, like glass or carbon fibres, and a flexible fibre or fibrillar network, like cellulose fibres or cellulose filaments. The thermoplastic resin can be, but not limited to, polyolefins, like polypropylene or polyethylene, or polyesters, like polylactic acid, or co-polymers, like acrylonitrile-butadiene-styrene terpolymer.

Abstract: A system and method automatically determines the physical memories inside a core or macro and their association with logical memories and their enabling signals. An integrated circuit (IC) source file that describes an integrated circuit in a hardware description language is received. The IC source file includes macros corresponding to memory. For each macro, a physical description file corresponding to the macro is generated. The description includes how the macro corresponds to the physical memory, associations of physical memories with the logical memory, enabling conditions, and data needed to test the memory.