Abstract: In a portable computing device having a node-based resource architecture, resource requests are batched or otherwise transactionized to help minimize inter-processing entity messaging or other messaging or provide other benefits. In a resource graph defining the architecture, each node or resource of the graph represents an encapsulation of functionality of one or more resources controlled by a processor or other processing entity, each edge represents a client request, and adjacent nodes of the graph represent resource dependencies. A single transaction of resource requests may be provided against two or more of the resources.

Abstract: In a portable computing device having a node-based resource architecture, a first or distributed node controlled by a first processor but corresponding to a second or native node controlled by a second processor is used to indirectly access a resource of the second node. In a resource graph defining the architecture each node represents an encapsulation of functionality of one or more resources, each edge represents a client request, and adjacent nodes represent resource dependencies. Resources defined by a first graph are controlled by the first processor but not the second processor, while resources defined by a second graph are controlled by the second processor but not the first processor. A client request on the first node may be received from a client under control of the first processor. Then, a client request may be issued on the second node in response to the client request on the first node.

Abstract: Systems and methods for measuring the effectiveness of a workload predictor operative on a mobile device are disclosed. A load manager includes a workload predictor, a sensor, an error generator and a controller. The workload predictor generates an estimate of the workload on a processor core operative on the mobile device. The sensor generates a measure of the actual workload on the processor core. The error generator receives the estimate of the workload and the measure of the actual workload on the processor core and generates an error signal. The controller receives the error signal and determines the effectiveness of the workload predictor as a function of the error signal over time.

Abstract: A mobile device, a method for managing and exposing a set of performance scaling algorithms on the device, and a computer program product are disclosed. The mobile device includes a multiple-core processor communicatively coupled to a non-volatile memory. The non-volatile memory includes a set of programs defined by a respective combination of a performance scaling algorithm and a set of parameters, a startup program that when executed by the multiple-core processor identifies at least one member of the set of programs suitable for monitoring operation of the mobile device and scaling the performance of an identified processor core and an application programming interface that exposes the set of programs.

Abstract: Systems and methods for optimizing performance scaling algorithms designated for operation on a mobile device are disclosed. A system memory includes program, use case, and results stores in addition to test logic. The program store contains a set of programs defined by the combination of a performance scaling algorithm and a set of parameters. The use case store contains information that identifies expected tasks to be performed by end users of the mobile device over time. The results store organizes a respective merit value determined after each of the set of programs has been executed for tasks defined by each use case. When executed, the test logic adjusts the mobile device and associates a select program for each of the use cases in response to the stored merit values. The merit values are determined as a function of a performance metric and a power metric.

Abstract: A method and system for determining optimal operating parameters for conserving power of a portable computing device may include plotting a hypersurface in a coordinate system. The method includes defining one or more axes in a coordinate system, such as a Cartesian coordinate system, that impact power consumption of a PCD and which may be held as constants when applied as workloads on CPU. Then, at least one axis is identified as an unknown or variable which may be optimized for power consumption. After the hypersurface containing optimized values is created for various workload scenarios for the PCD, workloads corresponding to the synthetic workloads described above are applied to the PCD. Workload predictors, like a DCVS algorithm, are executed by the PCD and are observed and compared to the hypersurface. Parameters for the workload predictor may be adjusted based on the values from the hypersurface.

Abstract: A method and system for managing resources of a portable computing device is disclosed. The method includes receiving node structure data for forming a node, in which the node structure data includes a unique name assigned to each resource of the node. A node has at least one resource and it may have multiple resources. Each resource may be a hardware or software element. The system includes a framework manger which handles the communications between existing nodes within a node architecture. The framework manager also logs activity of each resource by using its unique name. The framework manager may send this logged activity to an output device, such as a printer or a display screen. The method and system may help reduce or eliminate a need for customized APIs when a new hardware or software element (or both) are added to a portable computing device.

Abstract: A method and system for managing resources of a portable computing device is disclosed. The method includes receiving node structure data for forming a node, in which the node structure data includes a unique name assigned to each resource of the node. A node has at least one resource and it may have multiple resources. Each resource may be a hardware or software element. The method also includes receiving marker data and creating a marker. A marker includes a legacy element such as a hardware or software element. The system includes a framework manger which handles the communications between existing nodes and markers within a node architecture. The framework manager also logs activity of each resource and marker by using its unique name. The framework manager may send this logged activity to an output device, such as a printer or a display screen.

Abstract: A method of tuning a dynamic clock and voltage switching algorithm is disclosed and may include setting a default responsivity, determining whether a workload is registering after the workload is added, assigning a unique identifier to the workload if the workload is registering, and receiving a required responsivity from the workload.

Abstract: A method of utilizing a node power architecture (NPA) system, the method includes receiving a request to create a client, determining whether a resource is compatible with the request, and returning a client handle when the resource is compatible with the request.

Abstract: A method of executing a dynamic clock and voltage scaling (DCVS) algorithm in a central processing unit (CPU) is disclosed and may include monitoring CPU activity and determining whether a workload is designated as a special workload when the workload is added to the CPU activity.

Abstract: The aspects enable a computing device or microprocessor to determine a low power mode that provides the most system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Aspects provide a mechanism for determining an optimal low power configuration made up of a set of low power modes for the various resources within the computing device by determining which low power modes are valid at the time the processor enters an idle state, ranking the valid low power modes by expected power savings given the current device conditions, determining which valid low power mode provides the greatest power savings while meeting the latency requirements, and selecting a particular low power mode for each resource to enter.

Abstract: A method of sampling data within a central processing unit (CPU) is disclosed. The method may include monitoring CPU activity, determining whether the CPU enters idle, and executing a dynamic clock and voltage switching (DCVS) algorithm if the CPU enters idle.

Abstract: The aspects enable a computing device or microprocessor to determine a low-power mode that maximizes system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. The various aspects provide mechanisms and methods for compiling a plurality of low power resource modes to generate one or more synthetic low power resources from which can be selected an optimal low-power mode configuration made up of a set of selected synthetic low power resources.

Abstract: A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.

Abstract: A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle.

Abstract: A method of dynamically controlling a central processing unit is disclosed. The method may include determining when a CPU enters a steady state, calculating an optimal frequency for the CPU when the CPU enters a steady state, guaranteeing a steady state CPU utilization, and guaranteeing a steady state CPU utilization deadline.