Abstract: In view of defects in the prior art, the present disclosure provides a controller in a high-speed serial peripheral interface (SPI) master mode, where clock signals are provided by a phase locked loop (PLL), and the entire controller includes: a low-speed clock domain and a high-speed clock domain, where the PLL provides two main clock signals by different clock frequency dividers, provides a low-speed clock signal to the low-speed clock domain, and provides a high-speed source clock signal to the high-speed clock domain. By such technical solutions in the present disclosure, functions of different clock domains are divided through asynchronization of a high-speed SPI controller, and the function of a high-speed SPI flash access is implemented, thereby saving a read/write time. Especially in an application scenario of an SPI flash boot, the controller can greatly optimize a startup time.

Abstract: In view of defects in the prior art, the present disclosure provides a controller in a high-speed serial peripheral interface (SPI) master mode, where clock signals are provided by a phase locked loop (PLL), and the entire controller includes: a low-speed clock domain and a high-speed clock domain, where the PLL provides two main clock signals by different clock frequency dividers, provides a low-speed clock signal to the low-speed clock domain, and provides a high-speed source clock signal to the high-speed clock domain. By such technical solutions in the present disclosure, functions of different clock domains are divided through asynchronization of a high-speed SPI controller, and the function of a high-speed SPI flash access is implemented, thereby saving a read/write time. Especially in an application scenario of an SPI flash boot, the controller can greatly optimize a startup time.

Abstract: A deep standby method and device for and embedded system is disclosed, wherein the method mainly includes: a selecting step for selecting an available data swap block from the data swap area of a non-volatile memory as a deep standby block; a writing step for writing the current system data and state of the CPU into the deep standby block, and writing a deep standby flag into the deep standby block; and a shutting down step for making the system off to fall into a deep standby.

Abstract: A method and system for backward compatible multi-channel audio encoding and decoding in sense of the space information maximum entropy is disclosed. The technical solution according to the invention can adopt any existing stereo channel encoding system to encode the multi-channels audio signals, so as to transmit the multi-channel audio signals at the low bit rate as that of the stereo audio signals. More importantly, the existing stereo channel reproducing systems can also decode the audio format that is encoded utilizing the encoding method according to the invention.