Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and self-aligned contacts for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different oxidation and etch characteristics permits selective oxidation of only desired portions of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. The process and resulting structure affords inherently self-aligned gates and contacts for FET devices and conducting lines.