Patents by Inventor Nozomi Kido
Nozomi Kido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984484Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.Type: GrantFiled: September 9, 2021Date of Patent: May 14, 2024Assignee: Kioxia CorporationInventors: Tomonori Kajino, Taichi Iwasaki, Tatsuya Fujishima, Masayuki Shishido, Nozomi Kido
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Publication number: 20220310808Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.Type: ApplicationFiled: September 9, 2021Publication date: September 29, 2022Applicant: Kioxia CorporationInventors: Tomonori KAJINO, Taichi IWASAKI, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Nozomi KIDO
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Patent number: 10777574Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.Type: GrantFiled: March 12, 2019Date of Patent: September 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masayuki Shishido, Tatsuya Fujishima, Nozomi Kido, Tomonori Kajino
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Publication number: 20200091182Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.Type: ApplicationFiled: March 12, 2019Publication date: March 19, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Masayuki SHISHIDO, Tatsuya FUJISHIMA, Nozomi KIDO, Tomonori KAJINO
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Publication number: 20200066748Abstract: According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of insulating layers and a plurality of conductive layers are alternately stacked above a substrate, a pillar that penetrates the stacked body while extending in a stacking direction of the stacked body, and a semiconductor layer, a first insulating layer, a charge accumulation layer, and a second insulating layer, which are stacked on a side surface of the pillar in order from the pillar, wherein the semiconductor layer has an average grain size that is larger on a side nearer to the pillar and is smaller on a side nearer to the first insulating layer.Type: ApplicationFiled: December 4, 2018Publication date: February 27, 2020Applicant: Toshiba Memory CorporationInventors: Daisuke MATSUSHITA, Yui KAGI, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Nozomi KIDO, Tomonori KAJINO, Nobuhito KUGE
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Publication number: 20160079266Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a selection gate electrode, a semiconductor pillar, a first insulating member, a second insulating member, a third insulating member. The stacked body is provided on the substrate. The selection gate electrode is provided on the stacked body. The first insulating member divides the stacked body in a first direction. The second insulating member is provided in an area directly above the first insulating member and dividing the selection gate electrode in the first direction. The third insulating member is provided in a region other than the area directly above the first insulating member and dividing the selection gate electrode in the first direction. An average width of the second insulating member in the first direction is larger than an average width of the third insulating member in the first direction.Type: ApplicationFiled: March 13, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Nozomi KIDO, Masao IWASE, Tadashi IGUCHI
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Publication number: 20150243512Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first mask layer on a workpiece layer. The method further includes forming a concave portion in the workpiece layer by first etching using the first mask layer. The method further includes forming a second mask layer on the workpiece layer in which the concave portion is formed. The method further includes processing the concave portion of the workpiece layer by second etching using the second mask layer.Type: ApplicationFiled: May 30, 2014Publication date: August 27, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kazuki KISHI, Tadashi Iguchi, Nozomi Kido
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Publication number: 20140027838Abstract: According to one embodiment, the stair array includes a deep portion, one stair, and a plurality of stairs. The one stair is provided next to the deepest portion in the first direction and has a level difference of one step with the deepest portion. Each of the stairs has a level difference of a plurality of steps with a stair next in the first direction.Type: ApplicationFiled: July 25, 2013Publication date: January 30, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Nozomi Kido, Yosuke Komori
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Patent number: D1021712Type: GrantFiled: August 10, 2022Date of Patent: April 9, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Nozomi Hirai, Yuki Isogai, Kazuhiro Sato, Takuya Ishibashi, Kenji Kido