Patents by Inventor Nruthya Nagesh Prabhu

Nruthya Nagesh Prabhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock gating circuit
    Patent number: 10355674
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 16, 2019
    Assignee: ARM Limited
    Inventors: Anil Kumar Baratam, Nruthya Nagesh Prabhu, Yves Thomas Laplanche
  • Clock Gating Circuit
    Publication number: 20190028091
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Inventors: Anil Kumar Baratam, Nruthya Nagesh Prabhu, Yves Thomas Laplanche