Abstract: A fully digital phase aligner includes a control loop acting upon a delay line comprising at least a cascade of delay cells, each cell being individually configurable to produce one of two selectable propagation delays as a function of the logic state of a respective digital control signal. This is done by way of a shift register including a number of latches equal to the number of the cells of the delay line. An output tap of each latch of the shift register controls a respective delay cell of the delay line. A digital state machine in the control loop prevents any undesired oscillations.

Abstract: A method for regulating the duty cycle of an input clock signal includes producing a second clock signal using a first adjustable delay circuit for varying the duty cycle. The second clock signal is applied to first and second circuits for respectively increasing and decreasing the duty cycle of the second clock signal. The method further includes monitoring if the first circuitry increases the duty cycle or if the second circuitry reducing the duty cycle saturates first. The duty cycle introduced by the first adjustable delay circuit is modified until saturation of the first and second circuits occur at substantially the same time.

Abstract: An interface circuit for coupling the output of an integrated circuit designed for a relatively low supply voltage to a circuit designed to operate at a higher supply voltage employs a cascoded architecture and makes use of two purposely derived reference voltages. The circuit comprises a level rising stage, an output buffer stage (off chip driver stage), an overdrive stage for the pull-up device of the output buffer and a drain follower stage, the pull-up element of which is driven by a second output node of the level rising stage and the pull-down element of which is driven by the inverted input data stream.

Abstract: A null consumption CMOS switch which may be set by nonvolatile programming is formed by a pair of complementary transistors preferably having a common drain and a common gate. The common gate is coupled to the floating gate a programmable and erasable, nonvolatile memory cell. The common gate/floating gate coupling can be a unitary floating gate structure. The floating gate directly drives the ON or OFF states of the two complementary transistors. On an output node of the switch, represented by the common drain of the pair of transistors, a signal present on a source node of one or the other of the two complementary transistors is replicated. The state of charge of the floating gate, imposed by programming or erasing, may be such as to reach advantageously a potential higher than the supply voltage or lower than the ground potential of the circuit. Different embodiments, such as a polarity selection, a path selector, a TRISTATE selector, and a logic gate selector are described.

Abstract: An EEPROM cell with a single level gate structure is structured over at least three distinct active areas of the semiconducting substrate over which extend portions of the single isolated gate structure of the cell. A read transistor of the cell is formed in a distinct active area which is substantially isolated from the active area of the select transistor, wherein the thin dielectric tunnel layer is formed. Therefore the interface toward the external logic circuitry represented by the read transistor and the interface toward the programming circuitry are substantially isolated from each other. The read transistor may be designated to function at voltage and current levels compatible with the operating levels of the logic circuitry without interfering with the programming of the cell, thus eliminating the need for level regenerating stages.