Abstract: Disclosed herein are integrated circuit (IC) structures and methods for fabricating and testing such IC structures prior to dicing from a semiconductor wafer on which the IC structures are formed. In one example, a method for fabricating an IC structure includes contacting a first plurality of test pads of the IC structure with one or more test probes. The first plurality of test pads are disposed within or on a first dielectric layer within a scribe lane, i.e., a test region. A first metal layer is formed over the first plurality of test pads if a predefined test criteria is met as determined using information obtained through first plurality of test pads using the one or more test probes. The first metal layer is a layer formed in a die region of an IC die that is being fabricated in the wafer.

Abstract: Examples described herein generally relate to wafer testing and structures implemented on a wafer for wafer testing. In an example method for testing a wafer, power is applied to a first pad in a test site (TS) region on the wafer. The TS region is electrically connected to a device under test (DUT) region on the wafer. The DUT region includes a DUT. The TS region and DUT region are in a first and second scribe line, respectively, on the wafer. A third scribe line is disposed on the wafer between the TS region and the DUT region. A signal is detected from a second pad in the TS region on the wafer. The signal is at least in part a response of the DUT to the power applied to the first pad.

Abstract: Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.

Abstract: Examples described herein provide a method for reducing warpage when stacking semiconductor substrates. In an example, a first substrate is bonded with a second substrate to form a stack. The first substrate comprises a first semiconductor substrate, and the second substrate comprises a second semiconductor substrate. The second semiconductor substrate is thinned, and a first trench is etched into a backside of the thinned second semiconductor substrate. A first stressed material is deposited into the first trench.

Abstract: Examples described herein generally relate to testing of bonded wafers and structures implemented for such testing. In an example method, power is applied to a first pad on a stack of bonded wafers. A wafer of the stack includes a process control monitor (PCM) region that includes structure regions. Each structure region is a device under test region, dummy region, and/or chain interconnect region (CIR). The stack includes a serpentine chain test structure (SCTS) electrically connected between first and second metal features in the wafer in first and second CIRs, respectively, in the PCM region. The SCTS includes segments, one or more of which are disposed between neighboring structure regions in the PCM region that are not the first and second CIRs. A signal is detected from a second pad on the stack. The first and second pads are electrically connected to the first and second metal features, respectively.

Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

Abstract: Examples described herein provide determining skew of transistors on an integrated circuit. In an example, an integrated circuit includes a ring oscillator and first and second detector circuits. The ring oscillator includes serially connected buffers. Each buffer includes serially connected inverters that include transistors. A transistor of each buffer has a different strength of another transistor of the respective buffer. The first and second detector circuits are connected to different first and second tap nodes, respectively, along the serially connected buffers. The first detector circuit is configured to count a number of cycles of a reference clock that a cyclic signal on the first tap node is either a logically high or low level. The second detector circuit is configured to count a number of cycles of the reference clock that a cyclic signal on the second tap node is either a logically high or low level.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.

Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.

Abstract: Embodiments herein describe a memory cell (e.g., a SRAM memory cell) that includes power selection logic for disconnecting storage inverters from a reference voltage source when writing data into the cell. In one embodiment, the memory cells may be disposed long distances (e.g., more than 100 microns) from the data drivers in the integrated circuit which can result in the data lines having large RC time constants. In one embodiment, disconnecting the memory cells from a power supply may counter (or mitigate) the large RC time constants of the data lines.

Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.

Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

Abstract: In an example, a semiconductor assembly includes an integrated circuit (IC) die. The IC die includes a first region that includes a programmable fabric; a second region that includes input/output (IO) circuits; and a third region that includes a die seal disposed between the programmable fabric and the IO circuits.

Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

Abstract: A memory cell includes a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node; a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the memory cell; and an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes; wherein the memory cell comprises a two gate pitch memory cell.

Abstract: A system for protecting an integrated circuit (IC) from electrostatic discharge (ESD) events includes a sensing circuit that detects an occurrence of an ESD event on one of a plurality of power supply rails of the IC and, in response, outputs an alert signal identifying the occurrence of the ESD event. The system includes a driver circuit that, responsive to receiving the alert signal, outputs an enable signal, and a cascaded switch. The cascaded switch includes first and second gates disposed upon a channel located between a drain of the cascaded switch coupled to a first power supply rail and a source of the cascaded switch coupled to a second power supply rail. Each of the two gates receives the enable signal and, responsive to the enable signal, the cascaded switch closes to establish a coupling between the first power supply rail and the second power supply rail.

Abstract: An embedded inductor and a method for forming an inductor are described. Spaced apart first stripes are formed substantially parallel with respect to one another as part of a first metal layer. First contacts, second contacts, and third contacts in respective combination provide at least portions of posts. Spaced apart second stripes substantially parallel with respect to one another and to the first stripes are formed as part of a second metal layer located between the first metal layer and the second metal layer. The first stripes, the posts, and the second stripes in combination provide turns of a coil.