Patents by Inventor Numair AHMED
Numair AHMED has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250218910Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Shruti Sharma, Prithwish Chatterjee, Numair Ahmed, Yuxin Fang, Siddharth Alur Narasimha Krishna, Wei-Lun Jen, Mollie A. Stewart, Suresh T. Narute, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20250218924Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Prithwish Chatterjee, Shruti Sharma, Numair Ahmed, Yuxin Fang, Wei-Lun Jen, Siddharth Alur Narasimha Krishna, Mollie A. Stewart, Srinivas Venkata Ramanuja Pietambaram, Suresh T. Narute
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Publication number: 20250218925Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Shruti Sharma, Prithwish Chatterjee, Numair Ahmed, Yuxin Fang, Siddharth Alur Narasimha Krishna, Wei-Lun Jen, Mollie A. Stewart, Suresh T. Narute, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20250218911Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Shruti Sharma, Prithwish Chatterjee, Numair Ahmed, Yuxin Fang, Siddharth Alur Narasimha Krishna, Wei-Lun Jen, Mollie A. Stewart, Ali Lehaf, Steve S. Cho, Sang Ha Yoo, David A. Woodley, Srinivas Venkata Ramanuja Pietambaram, Farzaneh Saeedifard
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Publication number: 20250219002Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Shruti Sharma, Prithwish Chatterjee, Numair Ahmed, Yuxin Fang, Siddharth Alur Narasimha Krishna, Wei-Lun Jen, Mollie A. Stewart, Ali Lehaf, Steve S. Cho, Sang Ha Yoo, David A. Woodley, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20250219028Abstract: An apparatus is provided which comprises: a substrate core comprising a first core layer bonded with a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and wherein the first circuit component comprises a deep trench capacitor, and one or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Bohan Shan, Numair Ahmed, Nevin Erturk, Ziyin Lin, Ryan Carrazzone, Hongxia Feng, Hiroki Tanaka, Haobo Chen, Kyle Arrington, Jose Waimin, Srinivas Pietambaram, Gang Duan, Dingying Xu, Mohit Gupta, Brandon Marin, Xiaoying Guo, Clay Arrington
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Publication number: 20250210469Abstract: Embodiments disclosed herein comprise an apparatus. In an embodiment, the apparatus comprises a substrate with a first cavity into the substrate. In an embodiment, the first cavity has a first depth. In an embodiment, a second cavity is provided into the substrate, where the second cavity has a second depth that is different than the first depth. In an embodiment, a first die is in the first cavity, where the first die has a first thickness. In an embodiment, a second die is in the second cavity, where the second die has a second thickness that is different than the first thickness.Type: ApplicationFiled: December 20, 2023Publication date: June 26, 2025Inventors: Brandon C. MARIN, Numair AHMED, Srinivas Venkata Ramanuja PIETAMBARAM, Jeremy D. ECTON, Gang DUAN, Benjamin DUONG, Suddhasattwa NAD, Bohan SHAN
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Publication number: 20250192059Abstract: Embodiments disclosed herein include bridge structures for package substrates. In an embodiment, a package substrate comprises a substrate that is a dielectric material. In an embodiment, a cavity is formed into the substrate. A first pad is on a bottom surface of the cavity, and a die is at least partially in the cavity. In an embodiment, a via passes through at least a portion of a thickness of the die, and a second pad is on the die. In an embodiment, the second pad directly contacts the first pad, and the first pad is the only electrically conductive structure between the via and the second pad.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Brandon C. MARIN, Minglu LIU, Bohan SHAN, Bainye Francoise ANGOUA, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Numair AHMED, Jeremy D. ECTON, Benjamin DUONG, Hongxia FENG, Bai NIE, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Dingying David XU, Bin MU, Mohit GUPTA, Xiaoying GUO, Andrey GUNAWAN, Yingying ZHANG, Yosuke KANAOKA, Yosef KORNBLUTH, Aaditya Anand CANDADAI, Daniel ROSALES-YEOMANS, Jieying KONG, Shuqi LAI, Ao WANG, Joshua STACEY, Dilan SENEVIRATNE, Jade Sharee LEWIS
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Publication number: 20250112165Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Brandon Marin, Hiroki Tanaka, Robert May, Srinivas Pietambaram, Gang Duan, Suddhasattwa Nad, Numair Ahmed, Jeremy Ecton, Benjamin Taylor Duong, Bai Nie, Haobo Chen, Xiao Liu, Bohan Shan, Shruti Sharma, Mollie Stewart
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Patent number: 12224253Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material.Type: GrantFiled: September 20, 2021Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Xin Ning, Brandon C. Marin, Kyu Oh Lee, Siddharth K. Alur, Numair Ahmed, Brent Williams, Mollie Stewart, Nathan Ou, Cary Kuliasha
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Publication number: 20240395661Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a glass core layer having a first surface layer and a second surface layer; multiple channels within the glass core layer between the first surface and the second surface layer; and a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material, wherein a first surface of the RDL contacts the first surface of the glass core layer.Type: ApplicationFiled: May 25, 2023Publication date: November 28, 2024Inventors: Numair Ahmed, Suddhasattwa Nad, Mohammad Mamunur Rahman, Brandon C. Marin, Sashi S. Kandanur, Srinivas Venkata Ramanuja Pietambaram, Darko Grujicic, Gang Duan, Banjamin Duong
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Publication number: 20240327201Abstract: MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.Type: ApplicationFiled: March 29, 2023Publication date: October 3, 2024Inventors: Numair Ahmed, Mohammad Mamunur Rahman, Suddhasattwa Nad, Sashi Kandanur, Darko Grujicic, Benjamin Duong, Srinivas Pietambaram, Tarek Ibrahim, Whitney Bryks
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Publication number: 20240312853Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 14, 2023Publication date: September 19, 2024Inventors: Sashi S. KANDANUR, Srinivas V. PIETAMBARAM, Darko GRUJICIC, Brandon C. MARIN, Suddhasattwa NAD, Benjamin DUONG, Gang DUAN, Mohammad Mamunur RAHMAN, Numair AHMED
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Publication number: 20240312888Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 14, 2023Publication date: September 19, 2024Inventors: Sashi S. KANDANUR, Srinivas V. PIETAMBARAM, Darko GRUJICIC, Brandon C. MARIN, Suddhasattwa NAD, Benjamin DUONG, Gang DUAN, Mohammad Mamunur RAHMAN, Numair AHMED
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Publication number: 20240222018Abstract: Substrate package-integrated oxide capacitors and related methods are disclosed herein. An example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Inventors: Thomas Sounart, Henning Braunisch, Aleksandar Aleksov, Kristof Darmawikarta, Numair Ahmed, Darko Grujicic, Suddhasattwa Nad, Benjamin Duong, Marcel Wall, Shayan Kaviani
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Publication number: 20240105575Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Inventors: Jason M. GAMBA, Haifa HARIRI, Kristof DARMAWIKARTA, Srinivas V. PIETAMBARAM, Hiroki TANAKA, Kyle MCELHINNY, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Haobo CHEN, Bai NIE, Numair AHMED
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Publication number: 20230317642Abstract: A substrate for an electronic device may include a core. The substrate may include a passive electronic component. For instance, the substrate may include a continuous layer of molding material encapsulating the passive electronic component within the core. One or more through vias may extend between a first surface of the core and a second surface of the core. The substrate may include one or more layers coupled with the core. One or more component terminals may facilitate electrical communication between the passive electronic component and one or more of the first layer or the second layer.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Numair Ahmed, Cary Kuliasha, Kyu Oh Lee, Jung Kyu Han
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Patent number: 11735551Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.Type: GrantFiled: March 25, 2019Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Jimin Yao, Shawna Liff, Xin Yan, Numair Ahmed
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Publication number: 20230092492Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Xin Ning, Brandon C. Marin, Kyu Oh Lee, Siddharth K. Alur, Numair Ahmed, Brent Williams, Mollie Stewart, Nathan Ou, Cary Kuliasha
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Publication number: 20220199503Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Manish DUBEY, Guruprasad ARAKERE, Deepak KULKARNI, Sairam AGRAHARAM, Wei-Lun K. JEN, Numair AHMED, Kousik GANESAN, Amol D. JADHAV, Kyu-Oh LEE