Abstract: A method for fabricating seamless, tungsten filled, small diameter contact holes, has been developed. The process features initially creating a tungsten plug, in the small diameter contact hole, and filling or repairing, seams or voids in the tungsten plug, with an additional layer of selectively deposited tungsten.

Abstract: Self-aligned transistors, which may be either bipolar or field effect, are described. Three insulator layers are formed over the surface of a monocrystalline semiconductor substrate and are patterned to form a protective block over the location of the first element of the transistor. A doped conductive layer is formed upon the substrate and upon the protective block. A fourth insulator layer is formed on the doped conductive layer. Those portions of the doped conductive layer and the fourth insulator layer that are above the horizontal plane of the top of the third insulator layer are removed. The third insulator layer is removed from the protective block. The structure is heated to form the second and third elements by outdiffusion. Oxide spacers are formed adjacent to the protective block. The protective block is removed. A gate oxide is formed for a field effect transistor.

Abstract: A process for filling small diameter contact holes, with tungsten, has been developed. This process consists of using two consecutive tungsten depositions. A first tungsten layer, that will exhibit a fast removal rate in a specific dry etch chemistry, such as RIE, is used to coat the sidewalls of the small diameter contact hole. Next a second layer of tungsten, that will exhibit a significantly slower removal rate then the first tungsten layer, is used to completely fill the contact hole. Etchback, to remove unwanted material from areas outside the contact hole, does not significantly attack the second tungsten fill, in the contact hole, thus not aggravating any seams in the second tungsten fill that may have been created during the LPCVD tungsten, contact hole fill process.

Abstract: A method for fabricating seamless, tungsten filled, small diameter contact holes, has been developed. The process features initially creating a tungsten plug, in the small diameter contact hole, and filling or repairing, seams or voids in the tungsten plug, with an additional layer of selectively deposited tungsten.

Abstract: A method of forming self-aligned transistors which may be either bipolar or field effect, and resultant structures, are described. Three insulator layers are formed over the surface of a monocrystalline semiconductor substrate and are patterned to form a protective block over the location of the first element of the transistor. A doped conductive layer is formed upon the substrate and upon the protective block. A fourth insulator layer is formed on the doped conductive layer. Those portions of the doped conductive layer and the fourth insulator layer that are above the horizontal plane of the top of the third insulator layer are removed. The third insulator layer is removed from the protective block. The structure is heated to form the second and third elements by outdiffusion. Oxide spacers are formed adjacent to the protective block. The protective block is removed. A gate oxide is formed for a field effect transistor.

Abstract: A method of forming self-aligned transistors which may be either bipolar or field effect is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be polycrystalline silicon, tungsten silicide, titanium nitride or the like. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in at least the locations of the first element of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.

Abstract: A method of forming self-aligned transistors wherein both bipolar and field effect transistors are formed in the same Integrated Circuit simultaneously is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be typically polycrystalline silicon. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in the locations of the first element, the emitter for the bipolar and gate for the MOSFET, of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.

Abstract: A method of forming self-aligned transistors which may be either bipolar or field effect is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be polycrystalline silicon, tungsten silicide, titanium nitride or the like. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in at least the locations of the first element of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.

Abstract: A method of forming self-aligned transistors wherein both bipolar and field effect transistors are formed in the same Integrated Circuit simultaneously is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be typically polycrystalline silicon. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in the locations of the first element, the emitter for the bipolar and gate for the MOSFET, of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.

Abstract: In the manufacture of an integrated-circuit device, periodic interruption of grain growth during chemical vapor deposition of a metal film results in enhanced surface smoothness and ease of patterning. Interruption of grain growth is by deposition of an auxiliary material which, in the interest of high conductivity of the film, may be conductive, may form a conductive compound or alloy, or may be eliminated upon additional metal deposition. When the metal is tungsten, silicon is a preferred grain-growth interrupting material.

Abstract: A metallization scheme useful for integrated circuits uses a buffer layer to ensure that the etch back of a contact metal, such as tungsten, deposited over the buffer layer, can be controlled to form a complete tungsten plug in a via while the tungsten on the dielectric is completely removed. The buffer layer, once exposed, reacts with the plasma etch to form non-volatile compounds which decrease the free surface mobility of the etching species. This active species depletion thus decreases the etch rate of the tungsten within the vias. Continued exposure of unreacted buffer material is ensured by performing a sputter cleaning simultaneously with the plasma etch.

Abstract: Silicides are important for submicron VLSIC technology. Problems have been found in forming silicides by known techniques involving simply depositing a metal film and heating that metal to form a silicide layer. This invention solves the problems through recognition that polymeric contamination can be left on the surface from commonly-used previous reactive ion etch steps, and removes any such contamination to metal deposition by the additional step of heating in dry oxygen at a low temperature, such as 800 degrees Centigrade, before the contamination has been significantly hardened.