Abstract: The invention provides a dynamic random-access memory (DRAM) and an operation method thereof. The DRAM includes a memory cell array, a temperature sensor, and a refresh logic circuit. The temperature sensor senses a temperature of the DRAM. The refresh logic circuit enters a tRFC based on a refresh command issued by a memory controller to perform an automatic refresh operation on at least one memory cell row of the memory cell array. In a temperature-controlled refresh mode, the refresh logic circuit correspondingly adjusts a number of a plurality of tRAS periods in the tRFC according to a temperature sensing result of the temperature sensor. In a fine granularity refresh mode, the refresh logic circuit correspondingly adjusts the number of the tRAS periods in the tRFC according to a granularity specified by the memory controller.

Abstract: The invention provides a dynamic random-access memory (DRAM) and an operation method thereof. The DRAM includes a memory cell array, a temperature sensor, and a refresh logic circuit. The temperature sensor senses a temperature of the DRAM. The refresh logic circuit enters a tRFC based on a refresh command issued by a memory controller to perform an automatic refresh operation on at least one memory cell row of the memory cell array. In a temperature-controlled refresh mode, the refresh logic circuit correspondingly adjusts a number of a plurality of tRAS periods in the tRFC according to a temperature sensing result of the temperature sensor. In a fine granularity refresh mode, the refresh logic circuit correspondingly adjusts the number of the tRAS periods in the tRFC according to a granularity specified by the memory controller.

Abstract: A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a memory cell array, a refresh counter, a row hammer logic circuit, and a refresh logic circuit. The memory cell array includes a plurality of memory cell rows. The refresh counter provides a current refresh word line address. The row hammer logic circuit provides a victim word line address. The refresh logic circuit refreshes a target row during a first sub-period of a tRFC by using the current refresh word line address to perform an automatic refresh operation. The refresh logic circuit refreshes a victim row during a second sub-period of the same tRFC for row hammer protection by using the victim word line address.

Abstract: The present disclosure provides an operation method related to a post package repair (PPR) function in a dynamic random access memory (DRAM) device. The method for operating a post package repair (PPR) function of a memory device is disclosed. The method includes providing a memory bank, which includes a memory array and a sense amplifier adjacent to the memory array, wherein the memory array comprises at least one defective row and at least one associated row, and the at least one associated row is electrically connected to the sense amplifier by a plurality of bit lines. The method also includes arranging a redundant row adjacent to the memory array, wherein the redundant row is electrically connected to the sense amplifier by the plurality of bit lines.

Abstract: The present disclosure provides an operation method related to a post package repair (PPR) function in a dynamic random access memory (DRAM) device. The method for operating a post package repair (PPR) function of a memory device is disclosed. The method includes providing a memory bank, which includes a memory array and a sense amplifier adjacent to the memory array, wherein the memory array comprises at least one defective row and at least one associated row, and the at least one associated row is electrically connected to the sense amplifier by a plurality of bit lines. The method also includes arranging a redundant row adjacent to the memory array, wherein the redundant row is electrically connected to the sense amplifier by the plurality of bit lines.

Abstract: The present disclosure provides a method for refreshing a memory array. The method includes the following steps: generating a plurality of target row records respectively for a plurality of banks; generating a plurality of row address records based on the plurality of target row records; and performing a row-hammer-refreshing process based on the plurality of row address records.

Abstract: A method of verifying a hard post package repair (hPPR) includes steps as follows. A predetermined data background is written into a partial array of a volatile memory. First data are read out from a target row of the partial array of the volatile memory. The volatile memory is commanded to perform the hPPR on the target row. The predetermined data background is written into the partial array of the volatile memory anew after the hPPR has been performed. Second data are read out from a target row of the partial array of the volatile memory. The first data are compared with the second data to verify whether the hPPR fails.

Abstract: The present disclosure provides a method for refreshing a memory array. The method includes the following steps: generating a plurality of target row records respectively for a plurality of banks; generating a plurality of row address records based on the plurality of target row records; and performing a row-hammer-refreshing process based on the plurality of row address records.

Abstract: The present disclosure provides a row-determining circuit. The row-determining circuit includes a plurality of row latches and a target row generator connected to the plurality of row latches. The target row generator is configured to generate a plurality of target row records respectively for a plurality of banks and then send the plurality of target row records respectively to the plurality of row latches. The plurality of row latches are configured to generate a plurality of row address records based on the plurality of target row records.

Abstract: The present disclosure provides a row-determining circuit. The row-determining circuit includes a plurality of row latches and a target row generator connected to the plurality of row latches. The target row generator is configured to generate a plurality of target row records respectively for a plurality of banks and then send the plurality of target row records respectively to the plurality of row latches. The plurality of row latches are configured to generate a plurality of row address records based on the plurality of target row records.

Abstract: The present disclosure provides a target row generator. The target row generator includes a plurality of counting modules, a comparing module and a first processing module. Each of the plurality of counting modules is configured to generate a counting record, and includes a reset timer. The reset timer is configured to generate a reset signal to reset a corresponding one of the plurality of counting modules. The comparing module is connected to the plurality of counting modules and is configured to compare a plurality of counting records generated by the plurality of counting modules. The first processing module is connected to the comparing module and is configured to generate a target row record based on a comparison result from the comparing module. The quantity of the plurality of counting records is less than the quantity of the plurality of stressed rows.