Abstract: A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and provides an FD output signal. A summer is coupled to the PD and FD for summing the PD and FD output signals, and for providing a summer output signal. The CDR further comprises a voltage-controlled oscillator (VCO) for receiving a direct current signal and providing a recovered clock signal. A polyphase filter is coupled to each of the VCO, PD, and QP detector. A re-timer is coupled to the polyphase filter and provides a re-timed data signal, wherein the CDR circuit is on-chip and the polyphase filter converts clock signals into phase reference signals.

Abstract: The load of the cascode amplifier is varied by connecting another (secondary) load in parallel with the original load. The secondary load is connected through a MOSFET switch. During the High Gain Mode the MOSFET switch is OFF and the secondary load is electrically isolated from the main load, whereas in the Low Gain Mode the switch is turned ON and the secondary load appears across the primary load, reducing the effective load impedance. The secondary load is AC coupled such that the DC bias current does not pass through the secondary load and hence the Noise Figure (NF) and linearity (IIP3) performance are better in the Low Gain Mode. A number of such switchable loads can be connected across the load to obtain programmability.

Abstract: Game playing apparatus is disclosed comprising a game controller arranged to be held by a game player and a base station connected to or forming part of a game console, the controller and base station communicating over a wireless link and wherein the base station is provided with a loop aerial and the game controller is provided with either a dipole aerial or a loop aerial.