Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of a physical structure by a general-purpose processor, generating a plurality of particles, simulating a flight path of at least one of the particles by a hardware-accelerated processor different from the general-purpose processor, identifying a voxel unit in the voxel mesh that intersects the flight path by the hardware-accelerated processor, passing information describing a collision between the one of the particles and the voxel unit from the hardware-accelerated processor to the general-purpose processor, determining a reaction between the one of the particles and the voxel unit by the general-purpose processor, and adding an extra voxel unit adjacent to the voxel unit based on the determining of the reaction.

Abstract: A semiconductor structure includes a substrate, nanostructures, source/drain features, a gate structure, and inner spacers. The nanostructures are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are electrically connected to and on opposite sides of the nanostructures in an X-direction. The gate structure extends in a Y-direction and wraps around the nanostructures. The inner spacers are between the nanostructures in the Z-direction. Each of the inner spacers includes a soft core layer and a hard liner layer wrapping around the soft core layer.

Abstract: A semiconductor memory structure includes a substrate, a doped region in the substrate, a stack over the substrate, a column disposed over the substrate and penetrating the stack, a ferroelectric layer, and semiconductor layer between the ferroelectric layer and the column. The stack includes a plurality of conductive layers and a plurality of insulating layer alternately stacked. The column includes an isolation structure, a source structure and a drain structure. The semiconductor layer is separated from the substrate by the ferroelectric layer.

Abstract: A keratinocyte growth factor (KGF)-transdermal peptide (TP) fusion protein is provided. The amino acid sequence of the KGF-TP fusion protein is shown as SEQ ID NO: 12. The nucleotide sequence of a gene encoding the KGF-TP fusion protein is shown as SEQ ID NO: 8. A recombinant pGM3301 vector containing the gene is also provided. A preparation method and application of the KGF-TP fusion protein are also provided.

Abstract: According to one embodiment, a method, computer system, and computer program product for predicting the movement intentions of ships is provided. The present invention may include obtaining binocular camera visual data of a body of water; identifying physical objects in the body of water; generating feature point clouds of the physical objects in the body of water; performing instance segmentation on the generated feature point clouds; analyzing the generated feature point clouds; predicting the movement intentions of identified ships in the body of water based on the analyzed feature point clouds; and displaying the predicted movement intentions of the identified ships in the body of water on an augmented reality device.

Abstract: Embodiments are related to providing external device communication and localization for virtual reality based equipment using radio-frequency identification (RFID). At least two receivers and a transmitter are used to recognize an external device and determine a location of the external device relative to the headset, based on tags coupled to the external device. A three-dimensional (3D) model is downloaded of the external device based on information received by the at least two receivers from the tags. A location of the external device is matched to the 3D model based on the tags. A virtual image is displayed of the external device corresponding to the location of the external device.

Abstract: A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.

Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of at least one of the particles with a ray-tracing method, identifying a voxel unit in the voxel mesh that intersects the flight path, determining a surface reaction between the one of the particles and the voxel unit, and adding an extra voxel unit adjacent to the voxel unit based on the determining of the surface reaction.

Abstract: Provided is a composition containing water-soluble non-ionic polyurethane, comprising (a) 0.1-30 parts of water-soluble non-ionic polyurethane dispersions by weight; (b) 10-30 parts of decontaminating surfactants by weight; (c) 0.01-5 parts of conditioning agents by weight; and (d) 100 parts of aqueous carriers by weight. The composition in the present invention is used as shampoo, and can make hair naturally strong and extend the volumizing duration of hair.

Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.

Abstract: A method for forming a semiconductor memory structure includes following operations. A plurality of doped regions are formed in a semiconductor substrate. The doped regions are separated from each other. A stack including a plurality of first insulating layers and a plurality of second insulating layers alternately arranged is formed over the semiconductor substrate. A first trench is formed in the stack. The second insulating layers are replaced with a plurality of conductive layers. A second trench is formed. A charge-trapping layer and a channel layer are formed in the second trench. An isolation structure is formed to fill the second trench. A source structure and a drain structure are formed at two sides of the isolation structure.

Abstract: A magnetic tunnel junction (MTJ) structure and a memory cell are provided. The MTJ includes a barrier layer, a free layer and a metal oxide cap layer. The free layer is disposed on the barrier layer. The metal oxide cap layer is disposed on the free layer. The metal oxide cap layer has a first surface and a second surface opposite to the first surface. The first surface of the metal oxide cap layer is in contact with the free layer. In a direction of a thickness of the metal oxide cap layer, both of an oxygen concentration at the first surface of the metal oxide cap layer and an oxygen concentration at the second surface of the metal oxide cap layer are higher than an oxygen concentration in a middle portion of the metal oxide cap layer.

Abstract: A semiconductor device includes a substrate including a planar portion and a mesa portion over the planar portion; an oxide layer over the mesa portion; a ferroelectric material strip covering a protruding plane of the oxide layer and exposing a side plane of the oxide layer; and a gate strip over the ferroelectric material strip and overlapping the oxide layer.

Abstract: A method includes: providing a substrate including a planar portion and a mesa portion over the planar portion; depositing an oxide layer over the mesa portion; depositing a ferroelectric material strip over the oxide layer and aligned with the mesa portion; and depositing a gate strip crossing the ferroelectric material strip and over the oxide layer.

Abstract: An electronic device includes a printed circuit board, a semiconductor chip, and a shielding unit. The semiconductor chip is mounted and electrically connected to the printed circuit board, and includes a magnetic memory element. The shielding unit includes a magnetic material, and is mounted to the printed circuit board to at least partially cover the magnetic memory element so as to reduce interference from an external magnetic field on the magnetic memory element.

Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of a physical structure by a central processing unit (CPU), generating a batch of particles, simulating a flight path of one of the particles with a ray-tracing method by a parallel processing thread in a graphics processing unit (GPU), identifying a surface normal of a voxel unit in the voxel mesh that intersects the flight path by the parallel processing thread in the GPU, passing parameters describing the one of the particles hitting the voxel mesh from the GPU to the CPU, determining a surface reaction between the one of the particles and the voxel unit by the CPU, and updating the voxel mesh based on the determining of the surface reaction.

Abstract: Among other things, one or more techniques for simulating a process operation of a process tool are provided. In an embodiment, a voxel mesh is defined to represent a structure and a conformal surface mesh is defined for the voxel mesh. Direction dependent rates are determined for voxels in the voxel mesh using the conformal surface mesh. The voxel mesh is updated based on the direction dependent rates. The defining of the conformal surface mesh, the determining of the direction dependent rates, and the updating of the voxel mesh are iterated to simulate the process operation. A parameter of the voxel mesh is determined after simulating the process operation.

Abstract: According to one embodiment, a method, computer system, and computer program product for predicting the movement intentions of ships is provided. The present invention may include obtaining binocular camera visual data of a body of water; identifying physical objects in the body of water; generating feature point clouds of the physical objects in the body of water; performing instance segmentation on the generated feature point clouds; analyzing the generated feature point clouds; predicting the movement intentions of identified ships in the body of water based on the analyzed feature point clouds; and displaying the predicted movement intentions of the identified ships in the body of water on an augmented reality device.

Abstract: An MRAM cell block and a magnetic shielding structure for the MRAM cell block are incorporated into a metal interconnect of an integrated circuit (IC) device. The magnetic shielding structure may be provided by metallization layers and via layers having wires and vias that incorporate a magnetic shielding material. The magnetic shielding material may form the wires and vias, form a liner around the wires, or may be a layer of the wires. The wires and vias may also include a metal that is more conductive than the magnetic shielding material. The metal interconnect may include layers above or below the magnetic shielding structure that lack the magnetic shielding material and are more conductive. The MRAM cell block with the magnetic shielding structure is optionally provided as a standalone memory device or incorporated into a 3-D IC device that includes a second substrate having a conventional metal interconnect.

Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.