Patents by Inventor Nuo Zhang
Nuo Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964032Abstract: Disclosed by the present invention are an aqueous polyurethane functional mask substrate and an application thereof. Two kinds of water-based polyurethane dispersions are used as the main components of the mask substrate. The transdermal penetration and absorption of functional ingredients such as whitening, moisturizing and anti-aging ingredients in facial mask products are promoted by means of the special cross-linked structures of polyurethane films. During use, a mask is evenly applied to the face; and after the mask dries, the entire mask may be removed directly or removed after being moistened using water. The mask substrate according to the present invention is also applicable to body masks such as a hand mask, a neck mask and a back mask.Type: GrantFiled: November 9, 2018Date of Patent: April 23, 2024Assignees: WANHUA CHEMICAL GROUP CO., LTD., WANHUA CHEMICAL (NINGBO) CO., LTD.Inventors: Xiaoxiao Ji, Haidong Jia, Nuo Xu, Shan Liu, Yunling Liu, Jie Zhang, Xueshun Ji, Jiakuan Sun
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Patent number: 11068276Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.Type: GrantFiled: June 4, 2019Date of Patent: July 20, 2021Assignee: Intel CorporationInventors: Jiewen Yao, Vincent Zimmer, Nicholas Adams, Willard Wiseman, Giri Mudusuru, Nuo Zhang
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Patent number: 10592253Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.Type: GrantFiled: February 7, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Giri P. Mudusuru, Rangasai V. Chaganty, Chasel Chiu, Satya P. Yarlagadda, Nivedita Aggarwal, Nuo Zhang
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Publication number: 20190286450Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.Type: ApplicationFiled: June 4, 2019Publication date: September 19, 2019Applicant: Intel CorporationInventors: JIEWEN YAO, VINCENT ZIMMER, NICHOLAS ADAMS, WILLARD WISEMAN, GIRI MUDUSURU, NUO ZHANG
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Patent number: 10310865Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.Type: GrantFiled: December 27, 2013Date of Patent: June 4, 2019Assignee: Intel CorporationInventors: Jiewen Yao, Vincent Zimmer, Nicholas Adams, Willard Wiseman, Giri Mudusuru, Nuo Zhang
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Publication number: 20170147357Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.Type: ApplicationFiled: February 7, 2017Publication date: May 25, 2017Inventors: Giri P. Mudusuru, Rangasai V. Chaganty, Chasel Chiu, Satya P. Yarlagadda, Nivedita Aggarwal, Nuo Zhang
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Patent number: 9563437Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.Type: GrantFiled: June 27, 2014Date of Patent: February 7, 2017Assignee: Intel CorporationInventors: Giri P. Mudusuru, Rangasai V. Chaganty, Chasel Chiu, Satya P. Yarlagadda, Nivedita Aggarwal, Nuo Zhang
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Publication number: 20170003976Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.Type: ApplicationFiled: December 27, 2013Publication date: January 5, 2017Applicant: INTEL CORPORATIONInventors: JIEWEN YAO, VINCENT ZIMMER, NICHOLAS ADAMS, WILLARD WISEMAN, GIRI MUDUSURU, NUO ZHANG
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Publication number: 20150378747Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Giri P. Mudusuru, Rangasai V. Chaganty, Chasel Chiu, Satya P. Yarlagadda, Nivedita Aggarwal, Nuo Zhang